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S912XET256J2MAL Datasheet, PDF (696/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1)
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x001A R
PWMPER6 W
Bit 7
6
5
4
3
2
1
Bit 0
0x001B R
PWMPER7 W
Bit 7
6
5
4
3
2
1
Bit 0
0x001C R
PWMDTY0 W
Bit 7
6
5
4
3
2
1
Bit 0
0x001D R
PWMDTY1 W
Bit 7
6
5
4
3
2
1
Bit 0
0x001E R
PWMDTY2 W
Bit 7
6
5
4
3
2
1
Bit 0
0x001F R
PWMDTY3 W
Bit 7
6
5
4
3
2
1
Bit 0
0x0020 R
PWMDTY4 W
Bit 7
6
5
4
3
2
1
Bit 0
0x0021 R
PWMDTY5 W
Bit 7
6
5
4
3
2
1
Bit 0
0x0022 R
PWMDTY6 W
Bit 7
6
5
4
3
2
1
Bit 0
0x0023 R
PWMDTY7 W
Bit 7
6
5
4
3
2
1
Bit 0
0x0024 R
0
0
PWM7IN
PWMSDN W PWMIF
PWMIE
PWMLVL
PWMRSTRT
PWM7INL PWM7ENA
= Unimplemented or Reserved
Figure 19-2. PWM Register Summary (Sheet 3 of 3)
1. Intended for factory test purposes only.
19.3.2.1 PWM Enable Register (PWME)
Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx
bits are set (PWMEx = 1), the associated PWM output is enabled immediately. However, the actual PWM
waveform is not available on the associated PWM output until its clock source begins its next cycle due to
the synchronization of PWMEx and the clock source.
NOTE
The first PWM cycle after enabling the channel can be irregular.
MC9S12XE-Family Reference Manual Rev. 1.25
696
Freescale Semiconductor