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S912XET256J2MAL Datasheet, PDF (618/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family | |||
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Chapter 16 Freescaleâs Scalable Controller Area Network (S12MSCANV3)
1. Read: Anytime
Write: Anytime when not in initialization mode, except RSTAT[1:0] and TSTAT[1:0] ï¬ags which are read-only; write of 1 clears
ï¬ag; write of 0 is ignored
NOTE
The CANRFLG register is held in the reset state1 when the initialization
mode is active (INITRQ = 1 and INITAK = 1). This register is writable again
as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0).
Table 16-11. CANRFLG Register Field Descriptions
Field
Description
7
WUPIF
Wake-Up Interrupt Flag â If the MSCAN detects CAN bus activity while in sleep mode (see Section 16.4.5.5,
âMSCAN Sleep Mode,â) and WUPE = 1 in CANTCTL0 (see Section 16.3.2.1, âMSCAN Control Register 0
(CANCTL0)â), the module will set WUPIF. If not masked, a wake-up interrupt is pending while this ï¬ag is set.
0 No wake-up activity observed while in sleep mode
1 MSCAN detected activity on the CAN bus and requested wake-up
6
CSCIF
CAN Status Change Interrupt Flag â This ï¬ag is set when the MSCAN changes its current CAN bus status
due to the actual value of the transmit error counter (TEC) and the receive error counter (REC). An additional 4-
bit (RSTAT[1:0], TSTAT[1:0]) status register, which is split into separate sections for TEC/REC, informs the
system on the actual CAN bus status (see Section 16.3.2.6, âMSCAN Receiver Interrupt Enable Register
(CANRIER)â). If not masked, an error interrupt is pending while this ï¬ag is set. CSCIF provides a blocking
interrupt. That guarantees that the receiver/transmitter status bits (RSTAT/TSTAT) are only updated when no
CAN status change interrupt is pending. If the TECs/RECs change their current value after the CSCIF is
asserted, which would cause an additional state change in the RSTAT/TSTAT bits, these bits keep their status
until the current CSCIF interrupt is cleared again.
0 No change in CAN bus status occurred since last interrupt
1 MSCAN changed current CAN bus status
5-4
RSTAT[1:0]
Receiver Status Bits â The values of the error counters control the actual CAN bus status of the MSCAN. As
soon as the status change interrupt ï¬ag (CSCIF) is set, these bits indicate the appropriate receiver related CAN
bus status of the MSCAN. The coding for the bits RSTAT1, RSTAT0 is:
00 RxOK:
0 ⤠receive error counter < 96
01 RxWRN: 96 ⤠receive error counter < 128
10 RxERR: 128 ⤠receive error counter
11 Bus-off(1): 256 ⤠transmit error counter
3-2
TSTAT[1:0]
Transmitter Status Bits â The values of the error counters control the actual CAN bus status of the MSCAN.
As soon as the status change interrupt ï¬ag (CSCIF) is set, these bits indicate the appropriate transmitter related
CAN bus status of the MSCAN. The coding for the bits TSTAT1, TSTAT0 is:
00 TxOK: 0 ⤠transmit error counter < 96
01 TxWRN: 96 ⤠transmit error counter < 128
10 TxERR: 128 ⤠transmit error counter < 256
11 Bus-Off: 256 ⤠transmit error counter
1. The RSTAT[1:0], TSTAT[1:0] bits are not affected by initialization mode.
MC9S12XE-Family Reference Manual Rev. 1.25
618
Freescale Semiconductor
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