S912XET256J2MAL Datasheet, PDF (319/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 8 S12X Debug (S12XDBGV3) Module
Table 8-25. State2 —Sequencer Next State Selection (continued)
SC[3:0]
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Description
Any match triggers to state3
Any match triggers to Final State
Match3 triggers to State1....... Other matches have no effect
Match3 triggers to State3....... Other matches have no effect
Match3 triggers to Final State....... Other matches have no effect
Match0 triggers to State1....... Match1 triggers to State3....... Other matches have no effect
Match1 triggers to State3....... Match0 triggers Final State....... Other matches have no effect
Match0 triggers to State1....... Match2 triggers to State3....... Other matches have no effect
Match2 triggers to State3....... Match0 triggers Final State....... Other matches have no effect
Match1 triggers to State1....... Match3 triggers to State3....... Other matches have no effect
Match3 triggers to State3....... Match1 triggers Final State....... Other matches have no effect
Match2 triggers to State1..... Match3 trigger to Final State
Match2 has no affect, all other matches (M0,M1,M3) trigger to Final State
Reserved. (No match triggers state sequencer transition)
Reserved. (No match triggers state sequencer transition)
The trigger priorities described in Table 8-42 dictate that in the case of simultaneous matches, the match
on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to
final state has priority over all other matches.
8.3.2.7.3 Debug State Control Register 3 (DBGSCR3)
Address: 0x0027
7
6
5
4
R
0
0
0
0
W
Reset
0
0
0
0
= Unimplemented or Reserved
3
SC3
0
2
SC2
0
1
SC1
0
0
SC0
0
Figure 8-11. Debug State Control Register 3 (DBGSCR3)
Read: If COMRV[1:0] = 10
Write: If COMRV[1:0] = 10 and S12XDBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 10. The state control register three selects the
targeted next state whilst in State3. The matches refer to the match channels of the comparator match
control logic as depicted in Figure 8-1 and described in Section 8.3.2.8.1. Comparators must be enabled
by setting the comparator enable bit in the associated DBGXCTL control register.
Table 8-26. DBGSCR3 Field Descriptions
Field
3–0
SC[3:0]
Description
These bits select the targeted next state whilst in State3, based upon the match event.
MC9S12XE-Family Reference Manual Rev. 1.25
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