S912XET256J2MAL Datasheet, PDF (372/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 10 XGATE (S12XGATEV3)
10.3.1.16 XGATE Register 4 (XGR4)
The XGR4 register (Figure 10-18) provides access to the RISC core’s register 4.
Module Base +0x00028
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
XGR4
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-18. XGATE Register 4 (XGR4)
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Table 10-18. XGR4 Field Descriptions
Field
Description
15–0
XGATE Register 4 — The RISC core’s register 4
XGR4[15:0]
10.3.1.17 XGATE Register 5 (XGR5)
The XGR5 register (Figure 10-19) provides access to the RISC core’s register 5.
Module Base +0x0002A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
XGR5
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-19. XGATE Register 5 (XGR5)
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Table 10-19. XGR5 Field Descriptions
Field
Description
15–0
XGATE Register 5 — The RISC core’s register 5
XGR5[15:0]
MC9S12XE-Family Reference Manual Rev. 1.25
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