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S912XET256J2MAL Datasheet, PDF (353/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family | |||
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Chapter 10
XGATE (S12XGATEV3)
Table 10-1. Revision History
Revision
Number
V03.22
V03.23
V03.24
Revision Date
06 Oct 2005
14 Dec 2005
17 Jan 2006
Sections
Affected
10.9.2/10-463
Description of Changes
- Internal updates
- Updated code example
- Internal updates
10.1 Introduction
The XGATE module is a peripheral co-processor that allows autonomous data transfers between the
MCUâs peripherals and the internal memories. It has a built in RISC core that is able to pre-process the
transferred data and perform complex communication protocols.
The XGATE module is intended to increase the MCUâs data throughput by lowering the S12X_CPUâs
interrupt load.
Figure 10-1 gives an overview on the XGATE architecture.
This document describes the functionality of the XGATE module, including:
⢠XGATE registers (Section 10.3, âMemory Map and Register Deï¬nitionâ)
⢠XGATE RISC core (Section 10.4.1, âXGATE RISC Coreâ)
⢠Hardware semaphores (Section 10.4.4, âSemaphoresâ)
⢠Interrupt handling (Section 10.5, âInterruptsâ)
⢠Debug features (Section 10.6, âDebug Modeâ)
⢠Security (Section 10.7, âSecurityâ)
⢠Instruction set (Section 10.8, âInstruction Setâ)
10.1.1 Glossary of Terms
XGATE Request
A service request from a peripheral module which is directed to the XGATE by the S12X_INT
module (see Figure 10-1). Each XGATE request attempts to activate a XGATE channel at a certain
priority level.
XGATE Channel
The resources in the XGATE module (i.e. Channel ID number, Priority level, Service Request
Vector, Interrupt Flag) which are associated with a particular XGATE Request.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
353
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