S912XET256J2MAL Datasheet, PDF (631/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
Table 16-26. Message Buffer Organization
Offset
Address
Register
0x00X0 IDR0 — Identifier Register 0
0x00X1 IDR1 — Identifier Register 1
0x00X2 IDR2 — Identifier Register 2
0x00X3 IDR3 — Identifier Register 3
0x00X4 DSR0 — Data Segment Register 0
0x00X5 DSR1 — Data Segment Register 1
0x00X6 DSR2 — Data Segment Register 2
0x00X7 DSR3 — Data Segment Register 3
0x00X8 DSR4 — Data Segment Register 4
0x00X9 DSR5 — Data Segment Register 5
0x00XA DSR6 — Data Segment Register 6
0x00XB DSR7 — Data Segment Register 7
0x00XC
0x00XD
DLR — Data Length Register
TBPR — Transmit Buffer Priority Register⁽¹⁾
0x00XE TSRH — Time Stamp Register (High Byte)
0x00XF TSRL — Time Stamp Register (Low Byte)
1. Not applicable for receive buffers
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Figure 16-24 shows the common 13-byte data structure of receive and transmit buffers for extended
identifiers. The mapping of standard identifiers into the IDR registers is shown in Figure 16-25.
All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM-based implementation¹.
All reserved or unused bits of the receive and transmit buffers always read ‘x’.
1. Exception: The transmit buffer priority registers are 0 out of reset.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
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