S912XET256J2MAL Datasheet, PDF (210/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 3 Memory Mapping Control (S12XMMCV4)
In emulation single-chip mode, accesses to global addresses which are not occupied by the on-chip
resources (unimplemented areas) result in accesses to the external bus. CPU accesses to global addresses
which are occupied by external memory space result in an illegal access reset (system reset) in case of no
MPU error. BDM accesses to the external space are performed but the data will be undefined.
In single-chip modes accesses by the CPU (except for firmware commands) to any of the unimplemented
areas (see Figure 3-19) will result in an illegal access reset (system reset) in case of no MPU error. BDM
accesses to the unimplemented areas are allowed but the data will be undefined.
No misaligned word access from the BDM module will occur; these accesses are blocked in the BDM
module (Refer to BDM Block Guide).
Misaligned word access to the last location of RAM is performed but the data will be undefined.
Misaligned word access to the last location of any global page (64 Kbyte) by any global instruction, is
performed by accessing the last byte of the page and the first byte of the same page, considering the above
mentioned misaligned access cases.
The non-internal resources (unimplemented areas or external space) are used to generate the chip selects
(CS0,CS1,CS2 and CS3) (see Figure 3-19), which are only active in normal expanded, emulation
expanded (see Section 3.3.2.1, “MMC Control Register (MMCCTL0)).
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