S912XET256J2MAL Datasheet, PDF (189/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 3 Memory Mapping Control (S12XMMCV4)
• Simultaneous accesses to different resources¹ (internal, external, and peripherals) (see Figure 3-1 )
• Resolution of target bus access collision
• MCU operation mode control
• MCU security control
• Separate memory map schemes for each master CPU, BDM and XGATE
• ROM control bits to enable the on-chip FLASH or ROM selection
• Port replacement registers access control
• Generation of system reset when CPU accesses an unimplemented address (i.e., an address which
does not belong to any of the on-chip modules) in single-chip modes
3.1.3 S12X Memory Mapping
The S12X architecture implements a number of memory mapping schemes including
• a CPU 8 MByte global map, defined using a global page (GPAGE) register and dedicated 23-bit
address load/store instructions.
• a BDM 8 MByte global map, defined using a global page (BDMGPR) register and dedicated 23-
bit address load/store instructions.
• a (CPU or BDM) 64 KByte local map, defined using specific resource page (RPAGE, EPAGE and
PPAGE) registers and the default instruction set. The 64 KBytes visible at any instant can be
considered as the local map accessed by the 16-bit (CPU or BDM) address.
• The XGATE 64 Kbyte local map.
The MMC module performs translation of the different memory mapping schemes to the specific global
(physical) memory implementation.
3.1.4 Modes of Operation
This subsection lists and briefly describes all operating modes supported by the MMC.
3.1.4.1 Power Saving Modes
• Run mode
MMC is functional during normal run mode.
• Wait mode
MMC is functional during wait mode.
• Stop mode
MMC is inactive during stop mode.
3.1.4.2 Functional Modes
• Single chip modes
In normal and special single chip mode the internal memory is used. External bus is not active.
1. Resources are also called targets.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
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