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S912XET256J2MAL Datasheet, PDF (552/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family | |||
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
Module Base + 0x0023
R
W
Reset
7
PACNT7
0
6
PACNT6
0
5
PACNT5
0
4
PACNT4
0
3
PACNT3
0
2
PACNT2
0
1
PACNT1
0
0
PACNT0
0
Figure 14-39. Pulse Accumulators Count Register 2 (PACN2)
Read: Anytime
Write: Anytime
All bits reset to zero.
The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded to form the PACA 16-bit pulse
accumulator. When PACA in enabled (PAEN = 1 in PACTL), the PACN3 and PACN2 registers contents
are respectively the high and low byte of the PACA.
When PACN3 overï¬ows from 0x00FF to 0x0000, the interrupt ï¬ag PAOVF in PAFLG is set.
Full count register access will take place in one clock cycle.
NOTE
A separate read/write for high byte and low byte will give a different result
than accessing them as a word.
When clocking pulse and write to the registers occurs simultaneously, write
takes priority and the register is not incremented.
14.3.2.18 Pulse Accumulators Count Registers (PACN1 and PACN0)
Module Base + 0x0024
7
6
5
4
3
2
R
PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10)
W
Reset
0
0
0
0
0
0
1
PACNT1(9)
0
0
PACNT0(8)
0
Figure 14-40. Pulse Accumulators Count Register 1 (PACN1)
Module Base + 0x0025
R
W
Reset
7
PACNT7
0
Read: Anytime
Write: Anytime
6
PACNT6
5
PACNT5
4
PACNT4
3
PACNT3
2
PACNT2
1
PACNT1
0
0
0
0
0
0
Figure 14-41. Pulse Accumulators Count Register 0 (PACN0)
0
PACNT0
0
MC9S12XE-Family Reference Manual Rev. 1.25
552
Freescale Semiconductor
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