MC9S08QE16CLC Datasheet, PDF (39/350 Pages) Freescale Semiconductor, Inc – Low-power wireless applications, Gas, water and heater meters

Chapter 3 Modes of Operation
Table 3-2. BDM Enabled Stop Mode Behavior
CPU, Digital
Mode PPDC Peripherals, RAM
ICG
ADC
Regulator I/O Pins
RTI
FLASH
Stop3
x
Standby
Standby Active Optionally on Active States held Optionally on
3.6.4 LVD Enabled in Stop Mode
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. If the LVD is enabled in stop by setting the LVDE and the LVDSE bits, then the voltage
regulator remains active during stop mode. If the user attempts to enter stop2 with the LVD enabled for
stop, the MCU will instead enter stop3. Table 3-3 summarizes the behavior of the MCU in stop when the
LVD is enabled.
Table 3-3. LVD Enabled Stop Mode Behavior
CPU, Digital
Mode PPDC Peripherals, RAM
ICG
ADC
Regulator I/O Pins
RTI
FLASH
Stop3
x
Standby
Standby Off Optionally on Active States held Optionally on
3.6.5 On-Chip Peripheral Modules in Stop Modes
When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even
in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate,
clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.6.1, “Stop2
Mode,” and Section 3.6.2, “Stop3 Mode,” for specific information on system behavior in stop modes.
Table 3-4. Stop Mode Behavior
Peripheral
CPU
RAM
FLASH
Parallel Port Registers
ADC
ICG
IIC
RTI
SCI
SPI
TPM
Mode
Stop2
Off
Standby
Off
Off
Off
Off
Off
Optionally on³
Off
Off
Off
Stop3
Standby
Standby
Standby
Standby
Optionally On¹
Optionally On²
Standby
Optionally on³
Standby
Standby
Standby
MC9S08AC60 Series Data Sheet, Rev. 3
Freescale Semiconductor
39