MC9S08QE16CLC Datasheet, PDF (32/350 Pages) Freescale Semiconductor, Inc – Low-power wireless applications, Gas, water and heater meters

Chapter 2 Pins and Connections
external reset circuitry unnecessary. This pin is normally connected to the standard 6-pin background
debug connector so a development system can directly reset the MCU system. If desired, a manual external
reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset).
Whenever any reset is initiated (whether from an external signal or from an internal system), the reset pin
is driven low for approximately 34 cycles of f_{Self_reset}. The reset circuitry decodes the cause of reset and
records it by setting a corresponding bit in the system control reset status register (SRS).
In EMC-sensitive applications, an external RC filter is recommended on the reset pin. See Figure 2-5 for
an example.
2.3.4 Background/Mode Select (BKGD/MS)
While in reset, the BKGD/MS pin functions as a mode select pin. Immediately after reset rises the pin
functions as the background pin and can be used for background debug communication. While functioning
as a background/mode select pin, the pin includes an internal pullup device, input hysteresis, and no output
slew rate control. When the pin functions as a background pin, it includes a high current output driver.
When the pin functions as a mode select pin it is input only, and therefore does not include a standard
output driver.
If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset.
If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low
during the rising edge of reset which forces the MCU to active background mode.
The BKGD pin is used primarily for background debug controller (BDC) communications using a custom
protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC
clock could be as fast as the bus clock rate, so there should never be any significant capacitance connected
to the BKGD/MS pin that could interfere with background serial communications.
Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from
cables and the absolute value of the internal pullup device play almost no role in determining rise and fall
times on the BKGD pin.
2.3.5 ADC Reference Pins (V_REFH, V_REFL)
The V_REFH and V_REFL pins are the voltage reference high and voltage reference low inputs respectively
for the ADC module.
2.3.6 External Interrupt Pin (IRQ)
The IRQ pin is the input source for the IRQ interrupt and is also the input for the BIH and BIL instructions.
If the IRQ function is not enabled, this pin can still be configured as the TPMCLK (see the TPM chapter).
In EMC-sensitive applications, an external RC filter is recommended on the IRQ pin. See Figure 2-5 for
an example.
MC9S08AC60 Series Data Sheet, Rev. 3
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Freescale Semiconductor