MC9S08QE16CLC Datasheet, PDF (169/350 Pages) Freescale Semiconductor, Inc – Low-power wireless applications, Gas, water and heater meters

Internal Clock Generator (S08ICGV4)
— FLL engaged internal unlocked is a transition state that occurs while the FLL is attempting to
lock. The FLL DCO frequency is off target and the FLL is adjusting the DCO to match the
target frequency.
— FLL engaged internal locked is a state that occurs when the FLL detects that the DCO is locked
to a multiple of the internal reference.
• Mode 4 — FLL bypassed external (FBE)
In this mode, the ICG is configured to bypass the FLL and use an external clock as the clock source.
• Mode 5 — FLL engaged external (FEE)
The ICG’s FLL is used to generate frequencies that are programmable multiples of the external
clock reference.
— FLL engaged external unlocked is a transition state that occurs while the FLL is attempting to
lock. The FLL DCO frequency is off target and the FLL is adjusting the DCO to match the
target frequency.
— FLL engaged external locked is a state which occurs when the FLL detects that the DCO is
locked to a multiple of the internal reference.
10.1.3 Block Diagram
Figure 10-3 is a top-level diagram that shows the functional organization of the internal clock generation
(ICG) module. This section includes a general description and a feature list.
EXTAL
XTAL
V_DDA
(SEE NOTE 2)
V_SSA
(SEE NOTE 2)
ICG
OSCILLATOR (OSC)
WITH EXTERNAL REF
SELECT
ICGERCLK
FREQUENCY _DCO
LOCKED
REF
LOOP (FLL)
SELECT
CLOCK
SELECT
OUTPUT
ICGDCLK CLOCK
SELECT
IRG
INTERNAL ^{TYP 243 kHz}
REFERENCE _{8 MHz}
GENERATORS _RG
LOSS OF LOCK
AND CLOCK DETECTOR
ICGIRCLK
FIXED
CLOCK
SELECT
LOCAL CLOCK FOR OPTIONAL USE WITH BDC
/R
ICGOUT
FFE
ICGLCLK
NOTES:
1. See Table 10-1 for specific use of ICGOUT, FFE, ICGLCLK, ICGERCLK
2. Not all HCS08 microcontrollers have unique supply pins for the ICG. See the device pin assignments.
Figure 10-3. ICG Block Diagram
MC9S08AC60 Series Data Sheet, Rev. 3
Freescale Semiconductor
169