XR16C2852 Datasheet, PDF (9/42 Pages) Exar Corporation – 3.3V AND 5V DUART WITH 128-BYTE FIFO

XR16C2852
REV. 2.0.0
3.3V AND 5V DUART WITH 128-BYTE FIFO
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FIGURE 5. EXTERNAL CLOCK CONNECTION FOR
EXTENDED DATA RATE
External Clock
vcc
gnd
XTAL1
Each UART also has their own prescaler along with
the BRG. The prescaler is controlled by a software bit
in the MCR register. The MCR register bit-7 sets the
prescaler to divide the input crystal or external clock
by 1 or 4. The clock output of the prescaler goes to
the BRG. The BRG further divides this clock by a pro-
grammable divisor between 1 and (2¹⁶ -1) to obtain a
16X sampling rate clock of the serial data rate. The
sampling rate clock is used by the transmitter for data
bit shifting and receiver for data sampling.
VCC
R1
2K
XTAL2
FIGURE 6. BAUD RATE GENERATOR AND PRESCALER
XTAL1
XTAL2
C rysta l
Osc/
Buffer
P re s c a le r
Divide by 1
P re s c a le r
Divide by 4
DLL and DLM
R e g is te rs
M CR Bit-7=0
(default)
Baud Rate
G e n e ra to r
Logic
M CR Bit-7=1
16X
Sam pling
Rate Clock to
Transm itter
Programming the Baud Rate Generator Registers
DLM and DLL provides the capability of selecting the
operating data rate. Table 5 shows the standard data
rates available with a 14.7456 MHz crystal or external
clock at 16X sampling rate clock rate. When using a
non-standard data rate crystal or external clock, the
divisor value can be calculated for DLL/DLM with the
following equation.
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16)
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