XR16C2852 Datasheet, PDF (30/42 Pages) Exar Corporation – 3.3V AND 5V DUART WITH 128-BYTE FIFO

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3.3V AND 5V DUART WITH 128-BYTE FIFO
XR16C2852
REV. 2.0.0
EFR BIT-3
CONT-3
0
0
1
0
1
X
X
X
1
0
1
0
TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS
EFR BIT-2
CONT-2
EFR BIT-1
CONT-1
EFR BIT-0
CONT-0
TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL
0
0
0
No TX and RX flow control (default and reset)
0
X
X
No transmit flow control
0
X
X
Transmit Xon1, Xoff1
1
X
X
Transmit Xon2, Xoff2
1
X
X
Transmit Xon1 and Xon2, Xoff1 and Xoff2
X
0
0
No receive flow control
X
1
0
Receiver compares Xon1, Xoff1
X
0
1
Receiver compares Xon2, Xoff2
0
1
1
Transmit Xon1, Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1
1
1
Transmit Xon2, Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1
1
1
Transmit Xon1 and Xon2, Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0
1
1
No transmit flow control,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables IER
bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7
to be modified. After modifying any enhanced bits,
EFR bit-4 can be set to a logic 0 to latch the new val-
ues. This feature prevents legacy software from alter-
ing or overwriting the enhanced functions once set.
Normally, it is recommended to leave it enabled, logic
1.
• Logic 0 = modification disable/latch enhanced fea-
tures. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 5-7 are saved to retain the user settings.
After a reset, the IER bits 4-7, ISR bits 4-5, FCR
bits 4-5, and MCR bits 5-7are set to a logic 0 to be
compatible with ST16C550 mode (default).
• Logic 1 = Enables the above-mentioned register
bits to be modified by the user.
EFR[5]: Special Character Detect Enable
• Logic 0 = Special Character Detect Disabled
(default).
• Logic 1 = Special Character Detect Enabled. The
UART compares each incoming receive character
with data in Xoff-2 register. If a match exists, the
receive data will be transferred to FIFO and ISR bit-
4 will be set to indicate detection of the special
character. Bit-0 corresponds with the LSB bit of the
receive character. If flow control is set for compar-
ing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control
and special character work normally. However, if
flow control is set for comparing Xon2, Xoff2
(EFR[1:0]= ‘01’) then flow control works normally,
but Xoff2 will not go to the FIFO, and will generate
an Xoff interrupt and a special character interrupt, if
enabled via IER bit-5.
EFR[6]: Auto RTS Flow Control Enable
RTS# output may be used for hardware flow control
by setting EFR bit-6 to logic 1. When Auto RTS is se-
lected, an interrupt will be generated when the re-
ceive FIFO is filled to the programmed trigger level
and RTS de-asserts to a logic 1 at the next upper trig-
ger level. RTS# will return to a logic 0 when FIFO da-
ta falls below the next lower trigger level. The RTS#
output must be asserted (logic 0) before the auto RTS
can take effect. RTS# pin will function as a general
purpose output when hardware flow control is dis-
abled.
• Logic 0 = Automatic RTS flow control is disabled
(default).
• Logic 1 = Enable Automatic RTS flow control.
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