XR16C2852 Datasheet, PDF (22/42 Pages) Exar Corporation – 3.3V AND 5V DUART WITH 128-BYTE FIFO

áç
3.3V AND 5V DUART WITH 128-BYTE FIFO
XR16C2852
REV. 2.0.0
4.5.1 Interrupt Generation:
• LSR is by any of the LSR bits 1, 2, 3 and 4.
• RXRDY is by RX trigger level.
• RXRDY Time-out is by a 4-char plus 12 bits delay
timer.
• TXRDY is by TX trigger level or TX FIFO empty (or
transmitter empty in auto RS-485 control).
• MSR is by any of the MSR bits 0, 1, 2 and 3.
• Receive Xoff/Special character is by detection of a
Xoff or Special character.
• CTS# is when its transmitter toggles the input pin
(from low to high) during auto CTS flow control
enabled by EFR bit-7.
• RTS# is when its receiver toggles the output pin
(from low to high) during auto RTS flow control
enabled by EFR bit-6.
4.5.2 Interrupt Clearing:
• LSR interrupt is cleared by a read to the LSR regis-
ter (but flags and tags not cleared until character(s)
that generated the interrupt(s) has been emptied or
cleared from FIFO).
• RXRDY interrupt is cleared by reading data until
FIFO falls below the trigger level.
• RXRDY Time-out interrupt is cleared by reading
RHR.
• TXRDY interrupt is cleared by a read to the ISR
register or writing to THR.
• MSR interrupt is cleared by a read to the MSR reg-
ister.
• Xoff or Special character interrupt is cleared by a
read to ISR.
• RTS# and CTS# flow control interrupts are cleared
by a read to the MSR register.
PRIORITY
LEVEL BIT-5
1
0
2
0
3
0
4
0
5
0
6
0
7
1
-
0
TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL
ISR REGISTER STATUS BITS
SOURCE OF INTERRUPT
BIT-4 BIT-3 BIT-2 BIT-1
BIT-0
0
0
1
1
0 LSR (Receiver Line Status Register)
0
1
1
0
0 RXRDY (Receive Data Time-out)
0
0
1
0
0 RXRDY (Received Data Ready)
0
0
0
1
0 TXRDY (Transmit Ready)
0
0
0
0
0 MSR (Modem Status Register)
1
0
0
0
0 RXRDY (Received Xoff or Special character)
0
0
0
0
0 CTS#, RTS# change of state
0
0
0
0
1 None (default)
ISR[0]: Interrupt Status
• Logic 0 = An interrupt is pending and the ISR con-
tents may be used as a pointer to the appropriate
interrupt service routine.
• Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt
at interrupt priority levels (See Interrupt Source
Table 9).
ISR[5:4]: Interrupt Status
These bits are enabled when EFR bit-4 is set to a log-
ic 1. ISR bit-4 indicates that the receiver detected a
data match of the Xoff character(s). Note that once
set to a logic 1, the ISR bit-4 will stay a logic 1 until a
Xon character is received. ISR bit-5 indicates that
CTS# or RTS# has changed state.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are
disabled. They are set to a logic 1 when the FIFOs
are enabled.
4.6 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY
This register is used to enable the FIFOs, clear the
FIFOs, set the transmit/receive FIFO trigger levels,
and select the DMA mode. The DMA, and FIFO
modes are defined as follows:
22