XR16C2852 Datasheet, PDF (7/42 Pages) Exar Corporation – 3.3V AND 5V DUART WITH 128-BYTE FIFO

XR16C2852
REV. 2.0.0
3.3V AND 5V DUART WITH 128-BYTE FIFO
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TABLE 1: CHANNEL A AND B SELECT
CS#
CHSEL
1
X
0
1
0
0
FUNCTION
UART de-selected
Channel A selected
Channel B selected
2.5 CHANNEL A AND B INTERNAL REGISTERS
Each UART channel in the 2852 has a set of en-
hanced registers for control, monitoring and data
loading and unloading. The configuration register set
is compatible to those already available in the stan-
dard single 16C550 and dual ST16C2550. These
registers function as data holding registers (THR/
RHR), interrupt status and control registers (ISR/
IER), a FIFO control register (FCR), receive line sta-
tus and control registers (LSR/LCR), modem status
and control registers (MSR/MCR), programmable da-
ta rate (clock) divisor registers (DLL/DLM), and a user
accessible scratchpad register (SPR).
Beyond the general 16C2550 features and capabili-
ties, the 2852 offers enhanced feature registers (AFR,
EMSR, FLVL, EFR, Xon/Xoff 1, Xon/Xoff 2, FCTR,
TRG, FC) that provide automatic RTS and CTS hard-
ware flow control, Xon/Xoff software flow control, au-
tomatic RS-485 half-duplex direction output enable/
disable, FIFO trigger level control, FIFO level
counters, and simultaneous writes to both channels.
All the register functions are discussed in full detail
later in “UART INTERNAL REGISTERS” on page 18.
2.6 SIMULTANEOUS WRITE TO CHANNEL A AND B
During a write mode cycle, the setting of Alternate
Function Register (AFR) bit-0 to a logic 1 will override
the CHSEL selection and allows a simultaneous write
to both UART channel sections. This functional capa-
bility allow the registers in both UART channels to be
modified concurrently, saving individual channel ini-
tialization time. Caution should be considered, how-
ever, when using this capability. Any in-process serial
data transfer may be disrupted by changing an active
channel’s mode.
2.7 DMA MODE
The device does not support direct memory access.
The DMA Mode (a legacy term) in this document
doesn’t mean “direct memory access” but refers to
data block transfer operation. The DMA mode affects
the state of the RXRDY# A/B (MF# A/B becomes
RXRDY# A/B output when AFR[2:1] = ‘10’) and
TXRDY# A/B output pins. The transmit and receive
FIFO trigger levels provide additional flexibility to the
user for block mode operation. The LSR bits 5-6 pro-
vide an indication when the transmitter is empty or
has an empty location(s) for more data. The user can
optionally operate the transmit and receive FIFO in
the DMA mode (FCR bit-3=1). When the transmit and
receive FIFO are enabled and the DMA mode is dis-
abled (FCR bit-3 = 0), the 2852 is placed in single-
character mode for data transmit or receive operation.
When DMA mode is enabled (FCR bit-3 = 1), the user
takes advantage of block mode operation by loading
or unloading the FIFO in a block sequence deter-
mined by the programmed trigger level. In this mode,
the 2852 sets the TXRDY# pin when the transmit
FIFO becomes full, and sets the RXRDY# pin when
the receive FIFO becomes empty. The following table
shows their behavior. Also see Figures 18
through 23.
TABLE 2: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE
PINS
FCR BIT-0=0
(FIFO DISABLED)
RXRDY# A/B
0 = 1 byte.
1 = no data.
FCR BIT-0=1 (FIFO ENABLED)
FCR Bit-3 = 0
(DMA Mode Disabled)
0 = at least 1 byte in FIFO
1 = FIFO empty.
FCR Bit-3 = 1
(DMA Mode Enabled)
1 to 0 transition when FIFO reaches the trigger
level, or timeout occurs.
0 to 1 transition when FIFO empties.
TXRDY# A/B
0 = THR empty.
1 = byte in THR.
0 = FIFO empty.
1 = at least 1 byte in FIFO.
0 = FIFO has at least 1 empty location.
1 = FIFO is full.
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