XR16C2852 Datasheet, PDF (24/42 Pages) Exar Corporation – 3.3V AND 5V DUART WITH 128-BYTE FIFO

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3.3V AND 5V DUART WITH 128-BYTE FIFO
XR16C2852
REV. 2.0.0
TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION
FCTR FCTR FCR
BIT-5 BIT-4 BIT-7
FCR
BIT-6
FCR
BIT-5
FCR
RECEIVE
TRANSMIT
BIT-4 TRIGGER LEVEL TRIGGER LEVEL
COMPATIBILITY
0
0
0
0
1 (default) Table-A. 16C550, 16C2550,
0
0
1 (default)
16C2552, 16C554, 16C580
0
1
4
compatible.
1
0
8
1
1
14
0
1
0
0
0
1
1
0
1
1
0
0
8
0
1
16
1
0
24
1
1
28
16
Table-B. 16C650A compatible.
8
24
30
1
0
0
0
0
1
1
0
1
1
0
0
8
0
1
16
1
0
56
1
1
60
8
Table-C. 16C654 compatible.
16
32
56
1
1
X
X
X
X Programmable Programmable Table-D. 16C850, 16L2750,
via TRG
via TRG 16C2850, 16L2752, 16C854,
register.
register. 16C864, 16C872 compatible.
FCTR[7] = 0. FCTR[7] = 1.
4.7 LINE CONTROL REGISTER (LCR) - READ/WRITE
The Line Control Register is used to specify the asyn-
chronous data communication format. The word or
character length, the number of stop bits, and the par-
ity are selected by writing the appropriate bits in this
register.
LCR[1-0]: TX and RX Word Length Select
These two bits specify the word length to be transmit-
ted or received.
BIT-1
BIT-0
WORD LENGTH
0
0
5 (default)
0
1
6
1
0
7
1
1
8
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in con-
junction with the programmed word length.
BIT-2
WORD
LENGTH
STOP BIT LENGTH
(BIT TIME(S))
0
5,6,7,8
1 (default)
1
5
1-1/2
1
6,7,8
2
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The
parity bit is a simple way used in communications for
data integrity check. See Table 11 for parity selection
summary below.
• Logic 0 = No parity.
• Logic 1 = A parity bit is generated during the trans-
mission while the receiver checks for parity error of
the data character received.
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