XR16C2852 Datasheet, PDF (25/42 Pages) Exar Corporation – 3.3V AND 5V DUART WITH 128-BYTE FIFO

XR16C2852
REV. 2.0.0
3.3V AND 5V DUART WITH 128-BYTE FIFO
áç
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic
1, LCR BIT-4 selects the even or odd parity format.
• Logic 0 = ODD Parity is generated by forcing an
odd number of logic 1’s in the transmitted character.
The receiver must be programmed to check the
same format (default).
• Logic 1 = EVEN Parity is generated by forcing an
even number of logic 1’s in the transmitted charac-
ter. The receiver must be programmed to check the
same format.
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the
forced parity format.
• LCR BIT-5 = logic 0, parity is not forced (default).
• LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity
bit is forced to a logical 1 for the transmit and
receive data.
TABLE 11: PARITY SELECTION
LCR BIT-5 LCR BIT-4 LCR BIT-3 PARITY SELECTION
X
X
0
No parity
0
0
1
Odd parity
0
1
1
Even parity
1
0
1
Force parity to mark,
“1”
AFR[0]: Concurrent Write Mode
When this bit is set, the CPU can write concurrently to
the same register in both UARTs. This function is in-
tended to reduce the dual UART initialization time. It
can be used by the CPU when both channels are ini-
tialized to the same state. The external CPU can set
or clear this bit by accessing either register set.
When this bit is set, the channel select pin still selects
the channel to be accessed during read operations.
The user should ensure that LCR Bit-7 of both chan-
nels are in the same state before executing a concur-
rent write to the registers at address 0, 1, or 2.
• Logic 0 = No concurrent write (default).
• Logic 1 = Register set A and B are written concur-
rently with a single external CPU I/O write opera-
tion.
AFR[2:1]: MF# Output Select
These bits select a signal function for output on the
MF# A/B pins. These signal function are described
as: OP2#, BAUDOUT#, or RXRDY#. Only one signal
function can be selected at a time.
BIT-2
0
0
1
1
BIT-1
0
1
0
1
MF# FUNCTION
OP2# (default)
BAUDOUT#
RXRDY#
Reserved
1
1
1
Forced parity to
space, “0”
LCR[6]: Transmit Break Enable
• When enabled, the Break control bit causes a
break condition to be transmitted (the TX output is
forced to a “space’, logic 0, state). This condition
remains, until disabled by setting LCR bit-6 to a
logic 0.
• Logic 0 = No TX break condition (default).
• Logic 1 = Forces the transmitter output (TX) to a
“space”, logic 0, for alerting the remote receiver of a
line break condition.
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM) enable.
• Logic 0 = Data registers are selected. (default)
• Logic 1 = Divisor latch registers are selected.
4.8 ALTERNATE FUNCTION REGISTER (AFR) - READ/
WRITE
This register is used to select specific modes of MF#
operation and to allow both UART register sets to be
written concurrently.
AFR[7:3]: Reserved
All are initialized to logic 0.
4.9 MODEM CONTROL REGISTER (MCR) OR GEN-
ERAL PURPOSE OUTPUTS CONTROL - READ/
WRITE
The MCR register is used for controlling the serial/
modem interface signals or general purpose inputs/
outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the mo-
dem interface is not used, this output may be used as
a general purpose output.
• Logic 0 = Force DTR# output to a logic 1 (default).
• Logic 1 = Force DTR# output to a logic 0.
MCR[1]: RTS# Output
The RTS# pin is a modem control output and may be
used for automatic hardware flow control by enabled
by EFR bit-6. If the modem interface is not used, this
output may be used as a general purpose output.
• Logic 0 = Force RTS# output to a logic 1 (default).
• Logic 1 = Force RTS# output to a logic 0.
25