XR16C2852 Datasheet, PDF (3/42 Pages) Exar Corporation – 3.3V AND 5V DUART WITH 128-BYTE FIFO

XR16C2852
REV. 2.0.0
PIN DESCRIPTIONS
3.3V AND 5V DUART WITH 128-BYTE FIFO
áç
NAME
44-PLCC
PIN #
TYPE
DESCRIPTION
DATA BUS INTERFACE
A2
10
I Address data lines [2:0]. These 3 address lines select one of the internal registers in
A1
14
UART channel A/B during a data bus transaction.
A0
15
D7
9
I/O Data bus lines [7:0] (bidirectional).
D6
8
D5
7
D4
6
D3
5
D2
4
D1
3
D0
2
IOR#
24
I Input/Output Read Strobe (active low). The falling edge instigates an internal read
cycle and retrieves the data byte from an internal register pointed to by the address
lines [A2:A0]. The data byte is placed on the data bus to allow the host processor to
read it on the rising edge.
IOW#
20
I Input/Output Write Strobe (active low). The falling edge instigates an internal write
cycle and the rising edge transfers the data byte on the data bus to an internal regis-
ter pointed by the address lines.
CS#
18
I UART chip select (active low). This function selects channel A or B in accordance
with the logical state of the CHSEL pin. This allows data to be transferred between
the user CPU and the 2852.
CHSEL
16
I Channel Select - UART channel A or B is selected by the logical state of this pin when
the CS# pin is a logic 0. A logic 0 on the CHSEL selects the UART channel B while a
logic 1 selects UART channel A. Normally, CHSEL could just be an address line from
the user CPU such as A4. Bit-0 of the Alternate Function Register (AFR) can tempo-
rarily override CHSEL function, allowing the user to write to both channel register
simultaneously with one write cycle when CS# is low. It is especially useful during the
initialization routine.
INTA
INTB
34
O UART channel A or B Interrupt output (active high). A logic high indicates channel A
17
or B is requesting for service. For more details, see Figures 18- 23.
TXRDYA#
1
TXRDYB#
32
O UART channel A or B Transmitter Ready (active low). The output provides
the TX FIFO/THR status for transmit channel A or B. See Table 2 on page 7.
MODEM OR SERIAL I/O INTERFACE
MFA#
35
O Multi-Function Output Channel A. This output pin can function as the OP2A#, BAUD-
OUTA#, or RXRDYA# pin. One of these output signal functions can be selected by
the user programmable bits 1-2 of the Alternate Function Register (AFR). These sig-
nal functions are described as follows:
1) OP2A# - When OP2A# (active low) is selected, the MF# pin is a logic 0 when MCR
bit-3 is set to a logic 1 (see MCR bit-3). MCR bit-3 defaults to a logic 1 condition after
a reset or power-up.
2) BAUDOUTA# - When BAUDOUTA# function is selected, the 16X Baud rate clock
output is available at this pin.
3) RXRDYA# - RXRDYA# (active low) is intended for monitoring DMA data transfers.
See Table 2 on page 7 for more details.
3