XR16C2852 Datasheet, PDF (20/42 Pages) Exar Corporation – 3.3V AND 5V DUART WITH 128-BYTE FIFO

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3.3V AND 5V DUART WITH 128-BYTE FIFO
XR16C2852
REV. 2.0.0
TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS REG READ/
A2-A0 NAME WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
Baud Rate Generator Divisor
000
001
010
DLL RD/WR Bit-7
DLM RD/WR Bit-7
AFR RD/WR Rsvd
0 0 0 DREV RD
0 0 1 DVID RD
Bit-7
0
Bit-6
Bit-6
Rsvd
Bit-6
0
Bit-5
Bit-5
Rsvd
Bit-5
0
Bit-4
Bit-4
Rsvd
Bit-4
1
Bit-3
Bit-3
Rsvd
Bit-3
0
Bit-2 Bit-1 Bit-0
Bit-2
RXRDY#
Select
Bit-1
Bit-0 ^{LCR[7] = 1}
LCR ≠ 0xBF
Baudout# Concur-
Select rent Write
Bit-2
0
Bit-1
1
Bit-0
0
LCR[7] = 1
LCR ≠ 0xBF
DLL=0x00
DLM=0x00
Enhanced Registers
0 0 0 TRG WR Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
000
FC
RD Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
001
FCTR RD/WR RX/TX SCPAD
Mode Swap
Trig
Table
Bit-1
Trig
Table
Bit-0
Auto
RS485
Direction
Control
RX IR
Input
Inv.
Auto
RTS
Hyst
Bit-1
Auto
RTS
Hyst
Bit-0
010
EFR
RD/WR Auto
CTS
Enable
Auto
RTS
Enable
Special
Char
Select
Enable
IER [7:4],
ISR [5:4],
FCR[5:4],
MCR[7:5]
Soft-
ware
Flow
Cntl
Bit-3
Soft-
ware
Flow
Cntl
Bit-2
Soft-
ware
Flow
Cntl
Bit-1
Soft-
ware
Flow
Cntl
Bit-0
LCR=0XBF
1 0 0 XON1 RD/WR Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
1 0 1 XON2 RD/WR Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
1 1 0 XOFF1 RD/WR Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
1 1 1 XOFF2 RD/WR Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1 RECEIVE HOLDING REGISTER (RHR) - READ-
ONLY
See “Receiver” on page 11.
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-
ONLY
See “Transmitter” on page 10.
4.3 BAUD RATE GENERATOR DIVISORS (DLL AND
DLM) - READ/WRITE
The Baud Rate Generator (BRG) is a 16-bit counter
that generates the data rate for the transmitter. The
rate is programmed through registers DLL and DLM
which are only accessible when LCR bit-7 is set to ‘1’.
See “Programmable Baud Rate Generator” on page 8
for more details.
4.4 INTERRUPT ENABLE REGISTER (IER) - READ/
WRITE
The Interrupt Enable Register (IER) masks the inter-
rupts from receive data ready, transmit empty, line
status and modem status registers. These interrupts
are reported in the Interrupt Status Register (ISR).
4.4.1 IER versus Receive FIFO Interrupt Mode
Operation
When the receive FIFO (FCR BIT-0 = 1) and receive
interrupts (IER BIT-0 = 1) are enabled, the RHR inter-
rupts (see ISR bits 2 and 3) status will reflect the fol-
lowing:
A. The receive data available interrupts are issued
to the host when the FIFO has reached the pro-
grammed trigger level. It will be cleared when the
FIFO drops below the programmed trigger level.
B. FIFO level will be reflected in the ISR register
when the FIFO trigger level is reached. Both the
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