XR16C2852 Datasheet, PDF (21/42 Pages) Exar Corporation – 3.3V AND 5V DUART WITH 128-BYTE FIFO

XR16C2852
REV. 2.0.0
3.3V AND 5V DUART WITH 128-BYTE FIFO
áç
ISR register status bit and the interrupt will be
cleared when the FIFO drops below the trigger
level.
C. The receive data ready bit (LSR BIT-0) is set as
soon as a character is transferred from the shift
register to the receive FIFO. It is reset when the
FIFO is empty.
4.4.2 IER versus Receive/Transmit FIFO Polled
Mode Operation
When FCR BIT-0 equals a logic 1 for FIFO enable; re-
setting IER bits 0-3 enables the XR16C2852 in the
FIFO polled mode of operation. Since the receiver
and transmitter have separate bits in the LSR either
or both can be used in the polled mode by selecting
respective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in RHR or RX
FIFO.
B. LSR BIT-1 indicates an overrun error has oc-
curred and that data in the FIFO may not be valid.
C. LSR BIT 2-4 provides the type of receive data er-
rors encountered for the data byte in RHR, if any.
D. LSR BIT-5 indicates THR is empty.
E. LSR BIT-6 indicates when both the transmit FIFO
and TSR are empty.
F. LSR BIT-7 indicates a data error in at least one
character in the RX FIFO.
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when
RHR has a data character in the non-FIFO mode or
when the receive FIFO has reached the programmed
trigger level in the FIFO mode.
• Logic 0 = Disable the receive data ready interrupt
(default).
• Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is
issued whenever the THR becomes empty in the non-
FIFO mode or when data in the FIFO falls below the
programmed trigger level in the FIFO mode. If the
THR is empty when this bit is enabled, an interrupt
will be generated.
• Logic 0 = Disable Transmit Ready interrupt
(default).
• Logic 1 = Enable Transmit Ready interrupt.
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3 or 4 is a logic 1,
it will generate an interrupt to inform the host control-
ler about the error status of the current data byte in
FIFO. LSR bits 1-4 generate an interrupt immediately
when the character has been received.
• Logic 0 = Disable the receiver line status interrupt
(default).
• Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
• Logic 0 = Disable the modem status register inter-
rupt (default).
• Logic 1 = Enable the modem status register inter-
rupt.
IER[4]: Sleep Mode Enable (requires EFR bit-4 =
1)
• Logic 0 = Disable Sleep Mode (default).
• Logic 1 = Enable Sleep Mode. See Sleep Mode
section for further details.
IER[5]: Xoff Interrupt Enable (requires EFR bit-
4=1)
• Logic 0 = Disable the software flow control, receive
Xoff interrupt. (default)
• Logic 1 = Enable the software flow control, receive
Xoff interrupt. See Software Flow Control section
for details.
IER[6]: RTS# Output Interrupt Enable (requires
EFR bit-4=1)
• Logic 0 = Disable the RTS# interrupt (default).
• Logic 1 = Enable the RTS# interrupt. The UART
issues an interrupt when the RTS# pin makes a
transition from low to high.
IER[7]: CTS# Input Interrupt Enable (requires EFR
bit-4=1)
• Logic 0 = Disable the CTS# interrupt (default).
• Logic 1 = Enable the CTS# interrupt. The UART
issues an interrupt when CTS# pin makes a transi-
tion from low to high.
4.5 INTERRUPT STATUS REGISTER (ISR) - READ-
ONLY
The UART provides multiple levels of prioritized inter-
rupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with
six interrupt status bits. Performing a read cycle on
the ISR will give the user the current highest pending
interrupt level to be serviced, others are queued up to
be serviced next. No other interrupts are acknowl-
edged until the pending interrupt is serviced. The In-
terrupt Source Table, Table 9, shows the data values
(bit 0-5) for the interrupt priority levels and the inter-
rupt sources associated with each of these interrupt
levels.
21