XR16C2852 Datasheet, PDF (1/42 Pages) Exar Corporation – 3.3V AND 5V DUART WITH 128-BYTE FIFO

áç
XR16C2852
APRIL 2002
3.3V AND 5V DUART WITH 128-BYTE FIFO
REV. 2.0.0
GENERAL DESCRIPTION
The XR16C2852¹ (2852) is a dual universal asyn-
chronous receiver and transmitter (UART). The de-
vice operates at 3.3V and 5V and is pin-to-pin com-
patible to Exar’s ST16C2552 and XR16L2752. The
2852 register set is compatible to the ST16C2552
and the XR16C2752 enhanced features. It supports
the Exar’s enhanced features of 128 bytes of TX and
RX FIFOs, programmable FIFO trigger level and
FIFO level counters, automatic hardware (RTS/CTS)
and software flow control, automatic RS-485 half du-
plex direction control output and a complete modem
interface. Onboard registers provide the user with op-
erational status and data error flags. An internal loop-
back capability allows system diagnotics. Indepen-
dent programmable baud rate generators are provid-
ed in each channel to select data rates up to 3.125
Mbps at 5V. The 2852 is available in the 44-pin PLCC
package.
NOTE: 1 Covered by U.S. Patent #5,649,122 and #5,832,205
APPLICATIONS
• Portable Appliances
• Telecommunication Network Routers
• Ethernet Network Routers
• Cellular Data Devices
• Factory Automation and Process Controls
FEATURES
• Pin-to-pin compatible to Exar’s ST16C2552 and
XR16L2752
• Improved version of PC16C552
• Two independent UART channels
•Register set compatible to 16C550
•Up to 3 Mbps at 5V, and 2 Mbps at 3.3V
•Transmit and Receive FIFOs of 128 bytes
•Programmable TX and RX FIFO Trigger Levels
•Transmit and Receive FIFO Level Counters
•Automatic Hardware (RTS/CTS) Flow Control
•Selectable Auto RTS Flow Control Hysteresis
•Automatic Software (Xon/Xoff) Flow Control
•Automatic RS-485 Half-duplex Direction Control
Output
•Wireless Infrared (IrDA 1.0) Encoder/Decoder
•Automatic sleep mode
•Full modem interface
• Alternate Function Register
• Device Identification and Revision
• Crystal oscillator or external clock input
• 3.3 V or 5 V operation
• Industrial and commercial temperature ranges
• 44-PLCC package
FIGURE 1. XR16C2852 BLOCK DIAGRAM
A 2 :A 0
D 7 :D 0
IO R #
IOW #
CS#
CHSEL
IN T A
IN T B
TXRDYA#
TXRDYB#
MFA#
(O P 2A #,
BAUDOUTA#, or
RXRDYA#)
MFB#
(O P 2B #,
BAUDOUTB#, or
RXRDYB#)
Reset
8-bit Data
Bus
In te r fa c e
UART Channel A
UART
Regs
BRG
128 Byte TX FIFO
TX & RX
IR
ENDEC
128 Byte RX FIFO
UART Channel B
(same as Channel A)
Crystal Osc/Buffer
M odem Control Logic
3.3V or 5V VCC
GND
TXA (or TXIRA)
RXA (or RXIRA)
TXB (or TXIRB)
RXB (or RXIRB)
XTAL1
XTAL2
CTS#A/B, RI#A/B,
CD#A/B, DSR#A/B
DTR#A/B, RTS#A/B
EXAR Corporation 48720 Kato Road, Fremont CA, 94538 • [phone] • FAX [phone] • www.exar.com • [e-mail]