XR16C2852 Datasheet, PDF (27/42 Pages) Exar Corporation – 3.3V AND 5V DUART WITH 128-BYTE FIFO

XR16C2852
REV. 2.0.0
3.3V AND 5V DUART WITH 128-BYTE FIFO
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LSR[7]: Receive FIFO Data Error Flag
• Logic 0 = No FIFO error (default).
• Logic 1 = A global indicator for the sum of all error
bits in the RX FIFO. At least one parity error, fram-
ing error or break indication is in the FIFO data.
This bit clears when there is no more error(s) in any
of the bytes in the RX FIFO.
4.11 MODEM STATUS REGISTER (MSR) - READ ONLY
This register provides the current state of the modem
interface input signals. Lower four bits of this register
are used to indicate the changed information. These
bits are set to a logic 1 whenever a signal from the
modem changes state. These bits may be used as
general purpose inputs when they are not used with
modem signals.
MSR[0]: Delta CTS# Input Flag
• Logic 0 = No change on CTS# input (default).
• Logic 1 = The CTS# input has changed state since
the last time it was monitored. A modem status
interrupt will be generated if MSR interrupt is
enabled (IER bit-3).
MSR[1]: Delta DSR# Input Flag
• Logic 0 = No change on DSR# input (default).
• Logic 1 = The DSR# input has changed state since
the last time it was monitored. A modem status
interrupt will be generated if MSR interrupt is
enabled (IER bit-3).
MSR[2]: Delta RI# Input Flag
• Logic 0 = No change on RI# input (default).
• Logic 1 = The RI# input has changed from a logic 0
to a logic 1, ending of the ringing signal. A modem
status interrupt will be generated if MSR interrupt is
enabled (IER bit-3).
MSR[3]: Delta CD# Input Flag
• Logic 0 = No change on CD# input (default).
• Logic 1 = Indicates that the CD# input has changed
state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is
enabled (IER bit-3).
MSR[4]: CTS Input Status
CTS# pin may function as automatic hardware flow
control signal input if it is enabled and selected by Au-
to CTS (EFR bit-7). Auto CTS flow control allows
starting and stopping of local data transmissions
based on the modem CTS# signal. A logic 1 on the
CTS# pin will stop UART transmitter as soon as the
current character has finished transmission, and a
logic 0 will resume data transmission. Normally MSR
bit-4 bit is the compliment of the CTS# input. However
in the loopback mode, this bit is equivalent to the
RTS# bit in the MCR register. The CTS# input may be
used as a general purpose input when the modem in-
terface is not used.
MSR[5]: DSR Input Status
DSR# (active high, logical 1). Normally this bit is the
compliment of the DSR# input. In the loopback mode,
this bit is equivalent to the DTR# bit in the MCR regis-
ter. The DSR# input may be used as a general pur-
pose input when the modem interface is not used.
MSR[6]: RI Input Status
RI# (active high, logical 1). Normally this bit is the
compliment of the RI# input. In the loopback mode
this bit is equivalent to bit-2 in the MCR register. The
RI# input may be used as a general purpose input
when the modem interface is not used.
MSR[7]: CD Input Status
CD# (active high, logical 1). Normally this bit is the
compliment of the CD# input. In the loopback mode
this bit is equivalent to bit-3 in the MCR register. The
CD# input may be used as a general purpose input
when the modem interface is not used.
4.12 SCRATCH PAD REGISTER (SPR) - READ/WRITE
This is a 8-bit general purpose register for the user to
store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (de-
fault) after a reset or a power off-on cycle.
4.13 ENHANCED MODE SELECT REGISTER (EMSR)
This register replaces SPR (during a Write) and is ac-
cessible only when FCTR[6] = 1.
EMSR[1:0]: Receive/Transmit FIFO Count (Write-
Only)
When Scratchpad Swap (FCTR[6]) is asserted, EM-
SR bits 1-0 controls what mode the FIFO Level
Counter is operating in.
TABLE 12: SCRATCHPAD SWAP SELECTION
FCTR[6] EMSR[1] EMSR[0] Scratchpad is
0
X
X
Scratchpad
1
0
0
RX FIFO Counter Mode
1
0
1
TX FIFO Counter Mode
1
1
0
RX FIFO Counter Mode
1
1
1
Alternate RX/TX FIFO
Counter Mode
During Alternate RX/TX FIFO Counter Mode, the first
value read after EMSR bits 1-0 have been asserted
will always be the RX FIFO Counter. The second val-
ue read will correspond with the TX FIFO Counter.
The next value will be the RX FIFO Counter again,
then the TX FIFO Counter and so on and so forth.
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