XR16C2852 Datasheet, PDF (17/42 Pages) Exar Corporation – 3.3V AND 5V DUART WITH 128-BYTE FIFO

XR16C2852
REV. 2.0.0
3.3V AND 5V DUART WITH 128-BYTE FIFO
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2.21 INTERNAL LOOPBACK
The 2852 UART provides an internal loopback capa-
bility for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register
bit-4 to logic 1. All regular UART functions operate
normally. Figure 13 shows how the modem port sig-
nals are re-configured. Transmit data from the trans-
mit shift register output is internally routed to the re-
ceive shift register input allowing the system to re-
ceive the same data that it was sending. The TX pin
is held at logic 1 or mark condition while RTS# and
DTR# are de-asserted, and CTS#, DSR# CD# and
RI# inputs are ignored. Caution: the RX input must be
held to a logic 1 during loopback test else upon exit-
ing the loopback test the UART may detect and report
a false “break” signal.
FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B
Transmit Shift Register
(THR/FIFO)
VCC
MCR bit-4=1
Receive Shift Register
(RHR/FIFO)
VCC
RTS#
CTS#
VCC
DTR#
DSR#
RI#
CD#
OP1#
OP2#
TXA/TXB
RXA/RXB
RTSA#/RTSB#
CTSA#/CTSB
DTRA#/DTRB#
DSRA#/DSRB#
RIA#/RIB#
CDA#/CDB#
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