XR16C2852 Datasheet, PDF (6/42 Pages) Exar Corporation – 3.3V AND 5V DUART WITH 128-BYTE FIFO

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3.3V AND 5V DUART WITH 128-BYTE FIFO
XR16C2852
REV. 2.0.0
2.0 FUNCTIONAL DESCRIPTIONS
2.1 CPU INTERFACE
The CPU interface is 8 data bits wide with 3 address
lines and control signals to execute data bus read and
write transactions. The 2852 data interface supports
the Intel compatible types of CPUs and it is compati-
ble to the industry standard 16C550 UART. No clock
(oscillator nor external clock) is required to operate a
data bus transaction. Each bus cycle is asynchronous
using CS#, IOR# and IOW# signals. Both UART
channels share the same data bus for host opera-
tions. The data bus interconnections are shown in
Figure 3.
FIGURE 3. XR16C2852 DATA BUS INTERCONNECTIONS
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR#
IOW#
UART_CS#
UART_CHSEL
UART_INTA
UART_INTB
TXRDYA#
(RXRDYA#)
TXRDYB#
(RXRDYB#)
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR#
IOW#
VCC
TXA
RXA
DTRA#
RTSA#
UART
Channel A
CTSA#
DSRA#
CDA#
RIA#
(OP2A#)
(BAUDOUTA#)
CS#
CHSEL
INTA
INTB
UART
Channel B
TXB
RXB
DTRB#
RTSB#
CTSB#
TXRDYA#
(RXRDYA#)
TXRDYB#
(RXRDYB#)
DSRB#
CDB#
RIB#
(OP2B#)
(BAUDOUTB#)
VCC
Serial Interface of
RS-232, RS-485
Serial Interface of
RS-232, RS-485
UART_RESET
RESET
GND
2750int
Pins in parentheses become available through the MF# pin. MF# A/B becomes RXRDY# A/B when AFR[2:1] = '10'. MF# A/B becomes OP2# A/B
when AFR[2:1] = '00'. MF# A/B becomes BAUDOUT# A/B when AFR[1:0] = '01'.
.
2.2 DEVICE RESET
The RESET input resets the internal registers and the
serial interface outputs in both channels to their de-
fault state (see Table 16 on page 31). An active high
pulse of longer than 40 ns duration will be required to
activate the reset function in the device.
2.3 DEVICE IDENTIFICATION AND REVISION
The XR16C2852 provides a Device Identification
code and a Device Revision code to distinguish the
part from other devices and revisions. To read the
identification code from the part, it is required to set
the baud rate generator registers DLL and DLM both
to 0x00. Now reading the content of the DLM will pro-
vide 0x12 for the XR16C2852 and reading the con-
tent of DLL will provide the revision of the part; for ex-
ample, a reading of 0x01 means revision A.
2.4 CHANNEL A AND B SELECTION
The UART provides the user with the capability to bi-
directionally transfer information between an external
CPU and an external serial communication device. A
logic 0 on chip select pin (CS#) allows the user to se-
lect the UART and then using the channel select
(CHSEL) pin, the user can select channel A or B to
configure, send transmit data and/or unload receive
data to/from the UART. Individual channel select func-
tions are shown in Table 1.
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