XR16C2852 Datasheet, PDF (19/42 Pages) Exar Corporation – 3.3V AND 5V DUART WITH 128-BYTE FIFO

XR16C2852
REV. 2.0.0
3.3V AND 5V DUART WITH 128-BYTE FIFO
áç
.
TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS REG READ/
A2-A0 NAME WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
16C550 Compatible Registers
0 0 0 RHR RD Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
0 0 0 THR WR Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
001
IER RD/WR 0/
0/
0/
0/
Modem RX Line TX
RX
CTS Int. RTS Int. Xoff Int.
Enable Enable Enable
Sleep
Mode
Enable
Stat. Int.
Enable
Stat. Empty Data
Int.
Int
Int.
Enable Enable Enable
0 1 0 ISR RD FIFOs FIFOs
0/
0/
INT
INT INT INT _{LCR[7] = 0}
Enabled Enabled
Source Source Source Source
INT
INT
Source Source
Bit-3
Bit-2 Bit-1 Bit-0
Bit-5 Bit-4
010
FCR
WR RXFIFO RXFIFO 0/
0/
Trigger Trigger
TXFIFO TXFIFO
Trigger Trigger
DMA
Mode
Enable
TX
RX FIFOs
FIFO FIFO Enable
Reset Reset
011
100
LCR RD/WR Divisor Set TX Set Par- Even
Enable Break
ity
Parity
Parity
Enable
Stop
Bits
Word Word
Length Length
Bit-1 Bit-0
MCR RD/WR
0/
BRG
Pres-
caler
0/
IR Mode
ENable
0/
XonAny
Internal
Lopback
Enable
OP2#
Output
Control
Rsvd RTS# DTR#
(OP1#) Output Output
Control Control
1 0 1 LSR RD RX FIFO THR & THR
RX RX Fram- RX
RX
RX _{LCR[7] = 0}
Global TSR Empty Break ing Error Parity Over- Data
Error Empty
Error run Ready
Error
110
111
MSR RD
CD#
Input
SPR RD/WR Bit-7
1 1 1 EMSR WR Rsvd
RI#
Input
Bit-6
DSR#
Input
Bit-5
CTS#
Input
Bit-4
Rsvd
Auto
RTS
Hyst.
bit-3
Auto
RTS
Hyst.
bit-2
Delta
CD#
Bit-3
Rsvd
Delta Delta Delta
RI# DSR# CTS#
Bit-2
Bit-1
Bit-0
LCR[7] = 0
FCTR bit-
6=0
Rsvd
Rx/Tx
FIFO
Count
Rx/Tx
FIFO
Count
LCR[7] = 0
FCTR bit-6=1
1 1 1 FLVL RD Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
19