XRT83L314 Datasheet, PDF (74/84 Pages) Exar Corporation – 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT

XRT83L314
14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
CLOCK SELECT REGISTER
The input clock source is used to generate all the necessary clock references internally to the LIU. The
microprocessor timing is derived from a PLL output which is chosen by programming the Clock Select Bits in
register 0xE9h. Therefore, if the clock selection bits are being programmed, the frequency of the PLL output
will be adjusted accordingly. During this adjustment, it is important to "Not" write to any other bit location within
the same register while selecting the input/output clock frequency. For best results, register 0xE9h can be
broken down into two sub-registers with the MSB being bits D[7:4] and the LSB being bits D[3:0] as shown in
Figure 45. Note: Bits D[7:6] are reserved.
FIGURE 45. REGISTER 0XE9H SUB REGISTERS
MSB
D7
D6
D5
D4
ALLT1/E1, CLKCNTL
LSB
D3
D2
D1
D0
Clock Selection Bits
Programming Examples:
Example 1: Changing bits D[7:4]
If bits D[7:4] are the only values within the register that will change in a WRITE process, the microprocessor
only needs to initiate ONE write operation.
Example 2: Changing bits D[3:0]
If bits D[3:0] are the only values within the register that will change in a WRITE process, the microprocessor
only needs to initiate ONE write operation.
Example 3: Changing bits within the MSB and LSB
In this scenario, one must initiate TWO write operations such that the MSB and LSB do not change within ONE
write cycle. It is recommended that the MSB and LSB be treated as two independent sub-registers. One can
either change the clock selection (LSB) and then change bits D[5:4] (MSB) on the SECOND write, or vice-
versa. No order or sequence is necessary.
TABLE 50: MICROPROCESSOR REGISTER 0XE9H BIT DESCRIPTION
GLOBAL REGISTER (0XE9H)
BIT
NAME
FUNCTION
D7
Reserved This Register Bit is Not Used
D6
Reserved This Register Bit is Not Used
Register
Type
R/W
R/W
Default
Value
(HW reset)
0
0
70