XRT83L314 Datasheet, PDF (30/84 Pages) Exar Corporation – 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT

XRT83L314
14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
3.0 TRANSMIT PATH LINE INTERFACE
The transmit path of the XRT83L314 LIU consists of 14 independent T1/E1/J1 transmitters. The following
section describes the complete transmit path from TCLK/TPOS/TNEG inputs to TTIP/TRING outputs. A
simplified block diagram of the transmit path is shown in Figure 19.
FIGURE 19. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT PATH
TCLK
TPOS
TNEG
HDB3/B8ZS
Encoder
Tx Jitter
Attenuator
Timing
Control
Tx Pulse Shaper
& Pattern Gen
Line Driver
TTIP
TRING
3.1 TCLK/TPOS/TNEG Digital Inputs
In dual rail mode, TPOS and TNEG are the digital inputs for the transmit path. In single rail mode, TNEG has
no function and can be left unconnected. The XRT83L314 can be programmed to sample the inputs on either
edge of TCLK. By default, data is sampled on the falling edge of TCLK. To sample data on the rising edge of
TCLK, set TCLKE to "1" in the appropriate global register. Figure 20 is a timing diagram of the transmit input
data sampled on the falling edge of TCLK. Figure 21 is a timing diagram of the transmit input data sampled on
the rising edge of TCLK. The timing specifications are shown in Table 7.
FIGURE 20. TRANSMIT DATA SAMPLED ON FALLING EDGE OF TCLK
TCLK_R
TCLK_F
TCLK
TPOS
or
TNEG
T_SU
T_HO
FIGURE 21. TRANSMIT DATA SAMPLED ON RISING EDGE OF TCLK
TCLK_F
TCLK_R
TCLK
TPOS
or
TNEG
T_SU
T_HO
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