XRT83L314 Datasheet, PDF (23/84 Pages) Exar Corporation – 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT

XRT83L314
14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
2.6 Clock and Data Recovery
The receive clock (RCLK) is recovered by the clock and data recovery circuitry. An internal PLL locks on the
incoming data stream and outputs a clock that’s in phase with the incoming signal. This allows for multi-
channel T1/E1/J1 signals to arrive from different timing sources and remain independent. In the absence of an
incoming signal, RCLK maintains its timing by using the internal master clock as its reference. The recovered
data can be updated on either edge of RCLK. By default, data is updated on the rising edge of RCLK. To
update data on the falling edge of RCLK, set RCLKE to "1" in the appropriate global register. Figure 9 is a
timing diagram of the receive data updated on the rising edge of RCLK. Figure 10 is a timing diagram of the
receive data updated on the falling edge of RCLK. The timing specifications are shown in Table 5.
FIGURE 9. RECEIVE DATA UPDATED ON THE RISING EDGE OF RCLK
R _DY
RCLK_R
RCLK_F
RCLK
RPOS
or
RNEG
R_OH
FIGURE 10. RECEIVE DATA UPDATED ON THE FALLING EDGE OF RCLK
R_DY
RCLK_F
RCLK_R
RCLK
RPOS
or
RNEG
R_OH
19