XRT83L314 Datasheet, PDF (50/84 Pages) Exar Corporation – 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT

XRT83L314
14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
FIGURE 42. INTEL µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS
ALE = 1
ADDR[10:0]
CS
DATA[7:0]
RD
WR
RDY
t₀
t₁
READ OPERATION
Valid Address
Valid Data for Readback
t₂
t₀
t₃
WRITE OPERATION
Valid Address
Data Available to Write Into the LIU
t₄
TABLE 18: INTEL MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS
SYMBOL
PARAMETER
MIN
MAX
t₀
Valid Address to CS Falling Edge
t₁
CS Falling Edge to RD Assert
t₂
RD Assert to RDY Assert
NA
RD Pulse Width (t₂)
t₃
CS Falling Edge to WR Assert
t₄
WR Assert to RDY Assert
NA
WR Pulse Width (t₄)
0
-
30
-
-
150
150
-
30
-
-
150
150
-
UNITS
ns
ns
ns
ns
ns
ns
ns
46