XRT83L314 Datasheet, PDF (71/84 Pages) Exar Corporation – 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT

XRT83L314
14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
TABLE 46: MICROPROCESSOR REGISTER 0XE5H BIT DESCRIPTION
GLOBAL REGISTER (0XE5H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
LCV/OFLW Line Code Violation / Counter Overflow Monitor Select
R/W
0
This bit is used to select the monitoring activity between the LCV
and the counter overflow status. When the 16-bit LCV counter sat-
urates, the counter overflow condition is activated. By default, the
LCV activity is monitored by bit D4 in register 0x05h.
0 = Monitoring LCV
1 = Monitoring the counter overflow status
D6
CNTRDEN Line Code Violation Counter Read Enable
R/W
0
This bit enables the 16-bit LCV counter contents to be read from
bits D[7:0] in register 0xE8h. If a counter reaches full scale, it sat-
urates and remains at FFFFh until a reset is initiated in register
0xE6h. By default the LCV counter readback function is disabled.
0 = Disabled
1 = Enables the 16-bit LCV Counters for Readback
D5
Reserved This Register Bit is Not Used
R/W
0
D4
Reserved This Register Bit is Not Used
R/W
0
D3
LCVCH3 Line Code Violation Counter Select
R/W
0
D2
LCVCH2 These bits are used to select which channel is to be addressed for
D1
LCVCH1 ^{reading the contents in register 0xE8h. It is also used to address}
D0
LCVCH0 ^{the counter for a given channel when performing an update or}
reset on a per channel basis. By default, Channel 0 is selected.
0000 = None
0001 = Channel 0
0010 = Channel 1
0011 = Channel 2
0100 = Channel 3
0101 = Channel 4
0110 = Channel 5
0111 = Channel 6
1000 = Channel 7
1001 = Channel 8
1010 = Channel 9
1011 = Channel 10
1100 = Channel 11
1101 = Channel 12
1110 = Channel 13
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