XRT83L314 Datasheet, PDF(62/84 Page) Exar Corporation – 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT

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XRT83L314 Datasheet, PDF (62/84 Pages) Exar Corporation – 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT

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XRT83L314

14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT

REV. 1.0.0

NOTE: The GIE bit in the global register 0xE0h must be set to "1" in addition to the individual register bits to enable the

interrupt pin.

TABLE 30: MICROPROCESSOR REGISTER 0X05H BIT DESCRIPTION

CHANNEL 0-13 (0X05H-0XD5H)

BIT

NAME

FUNCTION

Type

Default

Value

(HW reset)

EQFLAG Equalizer Attenuation Flag

The equalizer attenuation flag is always active regardless if the

interrupt generation is disabled. This bit indicates the EQFLAG

activity. An interrupt will not occur unless the EQFLAGE is set to

"1" in the channel register 0x04h and GIE is set to "1" in the global

0 = No Alarm

1 = Equalizer Attenuation Flag is Set

DMO Digital Monitor Output

The digital monitor output is always active regardless if the inter-

rupt generation is disabled. This bit indicates the DMO activity. An

interrupt will not occur unless the DMOIE is set to "1" in the chan-

nel register 0x04h and GIE is set to "1" in the global register

0xE0h.

0 = No Alarm

1 = Transmit output driver has failures

FLS FIFO Limit Status

The FIFO limit status is always active regardless if the interrupt

generation is disabled. This bit indicates whether the RD/WR

pointers are within 3-Bits. An interrupt will not occur unless the

FLSIE is set to "1" in the channel register 0x04h and GIE is set to

"1" in the global register 0xE0h.

0 = No Alarm

1 = RD/WR FIFO pointers are within Â±3-Bits

LCV/OF Line Code Violation / Counter Overflow

This bit serves a dual purpose. By default, this bit monitors the line

code violation activity. However, if bit 7 in register 0xE5h is set to a

"1", this bit monitors the overflow status of the internal LCV

counter. An interrupt will not occur unless the LCV/OFIE is set to

"1" in the channel register 0x04h and GIE is set to "1" in the global

0 = No Alarm

1 = A line code violation, bipolar violation, or excessive zeros has

occurred

NLCD Network Loop Code Detection

The network loop code detection is always active regardless if the

interrupt generation is disabled. This bit indicates the NLCD activ-

ity. An interrupt will not occur unless the NLCDIE is set to "1" in the

channel register 0x04h and GIE is set to "1" in the global register

0xE0h.

0 = No Alarm

1 = Network loop code detected according to the mode selected in

channel register 0x03h

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