XRT83L314 Datasheet, PDF (67/84 Pages) Exar Corporation – 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT

XRT83L314
14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
BIT
D7
D[6:0]
TABLE 40: MICROPROCESSOR REGISTER 0X0FH BIT DESCRIPTION
NAME
CHANNEL 0-13 (0X0FH-0XDFH)
FUNCTION
Register
Type
Reserved This Register Bit is Not Used
X
8SEG[6:0] Segment Number Eight, Same Description as Register 0x08h
R/W
Default
Value
(HW reset)
0
TABLE 41: MICROPROCESSOR REGISTER 0XE0H BIT DESCRIPTION
GLOBAL REGISTER (0XE0H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
SR/DR Single Rail/Dual Rail Mode
R/W
0
This bit sets the LIU to receive and transmit digital data in a single
rail or a dual rail format.
0 = Dual Rail Mode
1 = Single Rail Mode
D6
ATAOS Automatic Transmit All Ones
R/W
0
If ATAOS is selected, an all ones pattern will be transmitted on any
channel that experiences an RLOS condition. If an RLOS condi-
tion does not occur, TAOS will remain inactive.
0 = Disabled
1 = Enabled
D5
RCLKE Receive Clock Data
R/W
0
0 = RPOS/RNEG data is updated on the rising edge of RCLK
1 = RPOS/RNEG data is updated on the falling edge of RCLK
D4
TCLKE Transmit Clock Data
R/W
0
0 = TPOS/TNEG data is sampled on the falling edge of TCLK
1 = TPOS/TNEG data is sampled on the rising edge of TCLK
D3
DATAP Data Polarity
0 = Transmit input and receive output data is active "High"
1 = Transmit input and receive output data is active "Low"
R/W
0
D2
Reserved This Register Bit is Not Used
R/W
0
63