XRT83L314 Datasheet, PDF (22/84 Pages) Exar Corporation – 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT

XRT83L314
14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
2.4 Equalizer Attenuation Flag
The ability to detect the amount of cable loss on the receiver inputs is enhanced by having the ability to
generate an interrupt by programming a pre-determined value for cable loss into the EQFLAG[5:0] global
register. This is particularly useful in long haul applications where it is necessary for the LIU to generate an
interrupt for a cable loss which is lower than the declaration of the RLOS feature (see the RLOS section in this
datasheet). If the contents of the EQFLAG[5:0] register bits are equal to or less than the contents in the cable
loss indicator bits CLOS[5:0] for a given channel, an interrupt will be generated (if enabled in the appropriate
channel register and GIE is to "1"). Using the same example in Figure 7, a simplified block diagram of the
equalizer flag is shown in Figure 8.
FIGURE 8. SIMPLIFIED BLOCK DIAGRAM OF THE EQUALIZER ATTENUATION FLAG
Receiver Inputs
RTIP/RRING
-25dB of Cable
Loss
Equalizer and
Peak Detector
Read Only
CLOS[5:0] = 0x19h
EQFLAG[5:0] = 0x19h
Programmable
XRT83L314
If (CLOS = EQFLAG)
Generate an Interrupt
2.5 Peak Detector and Slicer
The peak detector provides feedback to the equalizer control circuit until the amplitude of the incoming signal is
at an appropriate level. Once this level is obtained, the slicer identifies the incoming signal as a "1" and passes
the raw data to the clock and data recovery circuit. The slicer threshold is selected by programming SL[1:0] in
the appropriate global register. Selecting the slicer level is shown in Table 4.
TABLE 4: SELECTING THE SLICER LEVEL FOR THE PEAK DETECTOR
SL[1:0]
SLICER LEVEL
0h (00)
50%
1h (01)
45%
2h (10)
55%
3h (11)
68%
18