XRT83L314 Datasheet, PDF (64/84 Pages) Exar Corporation – 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT

XRT83L314
14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
TABLE 31: MICROPROCESSOR REGISTER 0X06H BIT DESCRIPTION
CHANNEL 0-13 (0X06H-0XD6H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D4
LCV/OFIS Line Code Violation / Counter Overflow Status
0 = No change
1 = Change in status occurred
RUR
0
D3
NLCDIS Network Loop Code Detection Status
0 = No change
1 = Change in status occurred
RUR
0
D2
AISDIS Alarm Indication Signal Status
0 = No change
1 = Change in status occurred
RUR
0
D1
RLOSIS Receiver Loss of Signal Status
0 = No change
1 = Change in status occurred
RUR
0
D0
QRPDIS Quasi Random Pattern Detection Status
0 = No change
1 = Change in status occurred
RUR
0
NOTE: Any change in status will generate an interrupt (if enabled in channel register 0x04h and GIE is set to "1" in the
global register 0xE0h). The status registers are reset upon read (RUR).
TABLE 32: MICROPROCESSOR REGISTER 0X07H BIT DESCRIPTION
CHANNEL 0-13 (0X07H-0XD7H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved This Register Bit is Not Used
R/W
0
D6
FLSDET FIFO LIMIT STATUS DETECT
RO
0
The FLSDET is used to determine whether the receiver or trans-
mitter FIFO has reached its limit status. If both FIFOs reach their
limit capacity, this bit will be set to "1".
0 = Receive JA
1 = Transmit JA
D5
CLOS5 Cable Loss Indication
RO
0
D4
CLOS4 This 6-Bit binary word indicates the cable attenuation on the
D3
CLOS3 ^{receiver inputs RTIP/RRING within ±1dB with Bit 5 being the MSB.}
D2
CLOS2
D1
CLOS1
D0
CLOS0
60