XRT75L03D Datasheet, PDF (7/134 Pages) Exar Corporation – THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

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XRT75L03D
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0
9.5 A REVIEW OF THE CATEGORY I INTRINSIC JITTER REQUIREMENTS (PER TELCORDIA GR-253-CORE) FOR DS3 AP-
PLICATIONS ........................................................................................................................................................................ 110
TABLE 31: SUMMARY OF "CATEGORY I INTRINSIC JITTER REQUIREMENT PER TELCORDIA GR-253-CORE, FOR DS3
APPLICATIONS .................................................................................................................................. 110
9.5.1 DS3 De-Mapping Jitter ..................................................................................................................... 111
9.5.2 Single Pointer Adjustment .............................................................................................................. 111
Figure 48. Illustration of Single Pointer Adjustment Scenario ...................................................................... 111
9.5.3 Pointer Burst .................................................................................................................................... 112
9.5.4 Phase Transients ............................................................................................................................. 112
Figure 49. Illustration of Burst of Pointer Adjustment Scenario .................................................................... 112
Figure 50. Illustration of "Phase-Transient" Pointer Adjustment Scenario ................................................... 112
9.5.5 87-3 Pattern ...................................................................................................................................... 113
9.5.6 87-3 Add ............................................................................................................................................ 113
Figure 51. An Illustration of the 87-3 Continuous Pointer Adjustment Pattern ............................................. 113
9.5.7 87-3 Cancel ....................................................................................................................................... 114
Figure 52. Illustration of the 87-3 Add Pointer Adjustment Pattern .............................................................. 114
Figure 53. Illustration of 87-3 Cancel Pointer Adjustment Scenario ............................................................. 114
9.5.8 Continuous Pattern .......................................................................................................................... 115
9.5.9 Continuous Add .............................................................................................................................. 115
Figure 54. Illustration of Continuous Periodic Pointer Adjustment Scenario ............................................... 115
9.5.10 Continuous Cancel ........................................................................................................................ 116
Figure 55. Illustration of Continuous-Add Pointer Adjustment Scenario ....................................................... 116
Figure 56. Illustration of Continuous-Cancel Pointer Adjustment Scenario .................................................. 116
9.6 A REVIEW OF THE DS3 WANDER REQUIREMENTS PER ANSI T1.105.03B-1997. ............................................. 117
9.7 A REVIEW OF THE INTRINSIC JITTER AND WANDER CAPABILITIES OF THE XRT75L03D IN A TYPICAL SYSTEM APPLI-
CATION ............................................................................................................................................................................ 117
9.7.1 Intrinsic Jitter Test results .............................................................................................................. 117
TABLE 32: SUMMARY OF "CATEGORY I INTRINSIC JITTER TEST RESULTS" FOR SONET/DS3 APPLICATIONS ..... 117
9.7.2 Wander Measurement Test Results ............................................................................................... 118
9.8 DESIGNING WITH THE XRT75L03D ................................................................................................................. 118
9.8.1 How to design and configure the XRT75L03D to permit a system to meet the above-mentioned
Intrinsic Jitter and Wander requirements ..................................................................................................................... 118
Figure 57. Illustration of the XRT75L03D being connected to a Mapper IC for SONET De-Sync Applications ..
118
CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06 ................................................. 119
CHANNEL 1 ADDRESS LOCATION = 0X0E ......................................... 119
CHANNEL 2 ADDRESS LOCATION = 0X16 ......................................... 119
CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06 ................................................. 120
CHANNEL 1 ADDRESS LOCATION = 0X0E .............................................. 120
CHANNEL 2 ADDRESS LOCATION = 0X16 ............................................... 120
JITTER ATTENUATOR CONTROL REGISTER - (CHANNEL 0 ADDRESS LOCATION = 0X07 ............................... 120
CHANNEL 1 ADDRESS LOCATION = 0X0F .................................. 120
CHANNEL 2 ADDRESS LOCATION = 0X17 .................................. 120
9.8.2 Recommendations on Pre-Processing the Gapped Clocks (from the Mapper/ASIC Device) prior to
routing this DS3 Clock and Data-Signals to the Transmit Inputs of the XRT75L03D .............................................. 121
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 ................................ 121
CHANNEL 1 ADDRESS LOCATION = 0X0F ............................ 121
CHANNEL 2 ADDRESS LOCATION = 0X17 ............................ 121
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 ................................ 121
CHANNEL 1 ADDRESS LOCATION = 0X0F ........................... 121
CHANNEL 2 ADDRESS LOCATION = 0X17 ........................... 121
Figure 58. Illustration of MINOR PATTERN P1 ............................................................................................ 122
Figure 59. Illustration of MINOR PATTERN P2 ............................................................................................ 123
Figure 60. Illustration of Procedure which is used to Synthesize MAJOR PATTERN A .............................. 123
Figure 61. Illustration of MINOR PATTERN P3 ............................................................................................ 124
Figure 62. Illustration of Procedure which is used to Synthesize PATTERN B ........................................... 124
Figure 63. Illustration of the SUPER PATTERN which is output via the "OC-N to DS3" Mapper IC ............ 125
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