XRT75L03D Datasheet, PDF (27/134 Pages) Exar Corporation – THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

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XRT75L03D
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0
JITTER ATTENUATOR INTERFACE
42
JA1
I
Jitter Attenuator Select 1:
Please see the Description above for JA0
43
JATx/Rx
I
Jitter Attenuator in Transmit/Receive Path Select Input:
This input pin is used to configure the Jitter Attenuator to operate in either the
Transmit or Receive path within each of the three (3) channels of the
XRT75L03D.
"Low" - Configures the Jitter Attenuator within each channel to operate in the
Receive Path.
"High" - Configures the Jitter Attenuator within each channel to operate in the
Transmit Path.
NOTES:
1. The setting of this input pin applies globally to all three (3) channels of
the XRT75L03D.
2. This input pin is ignored and should be tied to GND if the XRT75L03D
is configured to operate in the Host Mode or if the Jitter Attenuators are
disabled.
MICROPROCESSOR SERIAL INTERFACE - (HOST MODE)
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
69
SDO/RxMON
I/O Microprocessor Serial Interface - Serial Data Output:
This pin serially outputs the contents of a specified on-chip Command Register
during READ Operations via the Microprocessor Serial Interface. The data
which is output via this pin is updated upon the falling edge of the SCLK clock
signal.
This output pin will be tri-stated upon completion of a given READ operation.
NOTE: This pin functions as the RxMON input pin if the XRT75L03D has been
configured to operate in the Hardware Mode.
68
SDI/RxON
I
Microprocessor Serial Interface - Serial Data Input:
This input pin functions as the Serial Data Input pin for the Microprocessor
Serial Interface. In particular, this input pin will accept all of the following data in
a serial manner during READ and WRITE operations with the Microprocessor
Serial Interface.
• The READ/WRITE indicator bit.
• The Address Value of the Targeted Command Register for this particular
READ or WRITE operation.
• The Data to be written into the targeted Command Register for a given
WRITE operation.
All data that is applied to this input will be sampled upon the rising edge of the
SCLK input clock signal.
NOTE: This input pin will function as the RxON input pin if the XRT75L03D has
been configured to operate in the Hardware Mode.
22