XRT75L03D Datasheet, PDF (19/134 Pages) Exar Corporation – THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

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XRT75L03D
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0
SYSTEM-SIDE RECEIVE OUTPUT AND RECEIVE CONTROL PINS
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
66
RxClkINV/
CS
I
Receive Clock Invert Input - Chip Selectl:
In Hardware Mode is pin is used to configure the Receive Sections of the three
(3) channels in the XRT75L03D to either output the recovered data via the
RPOS_n or RNEG_n/LCV_n output pins upon either the rising or falling edge of
the RCLK_n clock output signal.
"Low" - Configures each of the Receive Sections to output the recovered data
via the RPOS_n and RNEG_n/LCV_n output pins upon the rising edge of the
RCLK_n output clock signal.
"High" - Configures each of the Receive Sections to output the recovered data
via the RPOS_n and RNEG_n/LCV_n output pins upon the falling edge of the
RCLK_n output clock signal.
NOTES:
1. This input pin will function as the CS (Chip Select Input pin) of the
Microprocessor Serial Interface when the XRT75L03D has been
configured to operate in the Host Mode.
2. This configuration setting applies globally to all three (3) of the
channels within the XRT75L03D.
3. If the Receive Sections are configured to operate in the Single-Rail
Mode, then the LCV_n output pin will be updated on the user-selected
edge of the RCLK_n signal, per this configuration selection.
106
SFM_EN
I
Single Frequency Mode Enable:
This input pin is used to configure the XRT75L03D to operate in the SFM (Sin-
gle Frequency) Mode.
When this feature is invoked the Single-Frequency Mode Synthesizer will
become active. By applying a 12.288MHz clock signal to pin 109, STS-1CLK/
12M the XRT75L03D will, depending upon which mode the user has configured
each of the three channels, generate all of the appropriate clock signals (e.g.,
34.368MHz, 44.736MHz or 51.84. Further, the XRT75L03D internal circuitry
will route each of these synthesized clock signals to the appropriate nodes of
the corresponding three channels in the XRT75L03D.
"Low" - Disables the Single Frequency Mode. In this configuration setting, the
user is required to supply to the E3CLK, DS3CLK or STS-1CLK input pins all of
the relevant clock signals that are to be used within the chip.
"High" - Enables the Single-Frequency Mode. A 12.288MHz clock signal MUST
be applied to pin 109 (STS-1CLK/12M).
NOTE: This input pin is internally pulled low.
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