XRT75L03D Datasheet, PDF (26/134 Pages) Exar Corporation – THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

XRT75L03D
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REV. 1.0.0 THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
GENERAL CONTROL PINS
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
62
ICT
I In-Circuit Test Input:
Setting this pin "Low" causes all digital and analog outputs to go into a high-
impedance state to allow for in-circuit testing. For normal operation, set this pin
"High".
NOTE: This pin is internally pulled “High".
70
HOST/HW
I
HOST/Hardware Mode Select:
Tie this pin “High” to configure the XRT75L03D in HOST mode. Tie this “Low” to
configure in Hardware mode.
When the XRT75L03D is configured in HOST mode, the states of many of the
discrete input pins are controlled by internal register bits.
NOTE: This pin is internally pulled up.
CONTROL AND ALARM INTERFACE
PIN #
122
123
SIGNAL NAME
RXA
RXB
TYPE
****
****
DESCRIPTION
External Resistor of 3.01K Ω ± 1%.
Should be connected between RxA and RxB for internal bias.
External Resistor of 3.01K Ω ± 1%.
Should be connected between RxA and RxB for internal bias.
JITTER ATTENUATOR INTERFACE
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
44
JA0
I
Jitter Attenuator Select 0:
In Hardware Mode, this pin along with pin 42 configures the Jitter Attenuator as
shown in the table below.
JA0
JA1
Mode
0
0
FIFO Depth = 16 bits
0
1
FIFO Depth = 32 bits
1
0
SONET/SDH De-Sync
Mode
1
1
Jitter Attenuator Disabled
NOTES:
1. The setting of these input pins applies globally to all three (3) channels
in the XRT75L03D.
2. This input pin is ignored and should be tied to GND if the XRT75L03D
is configured to operate in the Host Mode.
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