XRT75L03D Datasheet, PDF (16/134 Pages) Exar Corporation – THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

XRT75L03D
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REV. 1.0.0 THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
SYSTEM-SIDE RECEIVE OUTPUT AND RECEIVE CONTROL PINS
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
57 RNEG_0/LCV_0
113 RNEG_1/LCV_1
52 RNEG_2/LCV_2
O Receive Negative Data Output/Line Code Violation Indicator -
Channel 0:
Receive Negative Data Output/Line Code Violation Indicator -
Channel 1:
Receive Negative Data Output/Line Code Violation Indicator -
Channel 2:
The function of these pins depends on whether the XRT75L03D is configured in
Single Rail or Dual Rail mode.
Dual-Rail Mode - Receive Negative Polarity Data Output
If the channel/device has been configured to operate in the Dual-Rail Mode,
then all negative-polarity data will be output via this output pin. The positive-
polarity data will be output via the corresponding RPOS_n output pin. In other
words, the Receive Section of the corresponding Channel will pulse this output
pin "High" for one period of RCLK_n anytime it receives a negative-polarity
pulse via the RTIP/RRING input pins.
The data that is output via this pin is updated upon a user-selectable edge of the
RCLK_n output clock signal.
Single-Rail Mode - Line Code Violation Indicator Output
If the channel/device has been configured to operate in the Single-Rail Mode,
then this particular output pin will function as the Line Code Violation indicator
output.
In this configuration, the Receive Section of the Channel will pulse this output
pin "High" for at least one RCLK period whenever it detects either an LCV (Line
Code Violation) or an EXZ (Excessive Zero Event).
The data that is output via this pin is updated upon a user-selectable edge of the
RCLK_n output clock signal.
56
RxClk_0
114
RxClk_1
51
RxClk_2
O Receive Clock Output - Channel 0:
Receive Clock Output - Channel 1:
Receive Clock Output - Channel 2:
This output pin functions as the Receive or recovered clock signal. All Receive
(or recovered) data will output via the RPOS_n and RNEG_n outputs upon the
user-selectable edge of this clock signal.
Additionally, if the device/channel has been configured to operate in the Single-
Rail Mode, then the RNEG_n/LCV_n output pins will also be updated upon the
user-selectable edge of this clock signal.
75
REQEN_0
95
REQEN_1
84
REQEN_2
I
Receive Equalization Enable Input - Channel 0:
Receive Equalization Enable Input - Channel 1:
Receive Equalization Enable Input - Channel 2:
These input pins are used to either enable or disable the Receive Equalizer
block within the Receive Section of the corresponding channel.
"Low" - Disables the Receive Equalizer within the corresponding channel.
"High" - Enables the Receive Equalizer within the corresponding channel.
NOTES:
1. For virtually all applications, it is recommend that this input pin be
pulled "High" and enable the Receive Equalizer.
2. This input pin ignored and should be tied to GND if the XRT75L03D
has been configured to operate in the Host Mode.
3. These input pins are internally pulled low.
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