XRT75L03D Datasheet, PDF (132/134 Pages) Exar Corporation – THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

XRT75L03D
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REV. 1.0.0 THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07
CHANNEL 1 ADDRESS LOCATION = 0X0F
CHANNEL 2 ADDRESS LOCATION = 0X17
BIT 7
R/O
0
BIT 6
Unused
R/O
0
BIT 5
R/O
0
BIT 4
BIT 3
SONET APS
Recovery
Time Disable
Ch_n
JA RESET
Ch_n
R/W
R/W
0
0
BIT 2
JA1 Ch_n
BIT 1
JA in Tx Path
Ch_n
BIT 0
JA0 Ch_n
R/W
R/W
R/W
0
1
1
NOTE: The user can only disable the "SONET APS Recovery Time Mode" if the XRT75L03D is operating in the Host Mode.
If the user is operating the XRT75L03D in the Hardware Mode, then the user will have NO ability to disable the
"SONET APS Recovery Time Mode" feature.
9.8.4 How should one configure the XRT75L03D, if one needs to support "Daisy-Chain" Testing at
the end Customer's site?
Daisy-Chain testing is emerging as a new requirements that many of our customers are imposing on our
SONET Mapper and LIU products. Many System Designer/Manufacturers are finding out that whenever their
end-customers that are evaluating and testing out their systems (in order to determine if they wish to move
forward and start purchasing this equipment in volume) are routinely demanding that they be able to test out
these systems with a single piece of test equipment. This means that the end-customer would like to take a
single piece of DS3 or STS-1 test equipment and (with this test equipment) snake the DS3 or STS-1 traffic
(that this test equipment will generate) through many or (preferably all) channels within the system. For
example, we have had request from our customers that (on a system that supports OC-192) our silicon be able
to support this DS3 or STS-1 traffic snaking through the 192 DS3 or STS-1 ports within this system.
After extensive testing, we have determined that the best approach to complying with test "Daisy-Chain"
Testing requirements, is to configure the Jitter Attenuator blocks (within each of the Channels within the
XRT75L03D) into the "32-Bit" Mode. The user can configure the Jitter Attenuator block (within a given channel
of the XRT75L03D) to operate in this mode by settings in the table below.
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07
CHANNEL 1 ADDRESS LOCATION = 0X0F
CHANNEL 2 ADDRESS LOCATION = 0X17
BIT 7
R/O
0
BIT 6
Unused
R/O
0
BIT 5
R/O
0
BIT 4
BIT 3
SONET APS
Recovery
Time Disable
Ch_n
JA RESET
Ch_n
R/W
R/W
0
0
BIT 2
JA1 Ch_n
BIT 1
JA in Tx Path
Ch_n
BIT 0
JA0 Ch_n
R/W
R/W
R/W
1
1
0
REFERENCES
1. TEST REPORT - AUTOMATIC PROTECTION SWITCHING (APS) RECOVERY TIME TESTING WITH THE
XRT94L43 DS3/E3/STS-1 TO STS-12 MAPPER IC - Revision C Silicon
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