XRT75L03D Datasheet, PDF (57/134 Pages) Exar Corporation – THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

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XRT75L03D
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0
TABLE 13: JITTER TRANSFER PASS MASKS
RATE
(KBITS)
MASK
F1
F2
F3
F4
A1(dB)
A2(dB)
(HZ)
(HZ)
(HZ)
(KHZ)
G.823
100
300
34368
ETSI-TBR-24
3K
800K
0.5
-19.5
44736
GR-499, Cat I
10
10k
-
15k
0.1
-
GR-499, Cat II
10
56.6k
-
300k
0.1
-
GR-253 CORE
10
40
-
15k
0.1
-
51840
GR-253 CORE
10
40k
-
400k
0.1
-
The jitter attenuator within the XRT75L03D meets the latest jitter attenuation specifications and/or jitter transfer
characteristics as shown in the Figure 24.
FIGURE 24. JITTER TRANSFER REQUIREMENTS AND JITTER ATTENUATOR PERFORMANCE
A1
A2
F1
F2
F3
F4
JIT T E R F R E Q U E N C Y (kH z)
6.3.1 JITTER GENERATION:
Jitter Generation is defined as the process whereby jitter appears at the output port of the digital equipment in
the absence of applied input jitter. Jitter Generation is measured by sending jitter free data to the clock and
data recovery circuit and measuring the amount of jitter on the output clock or the re-timed data. Since this is
essentially a noise measurement, it requires a definition of bandwidth to be meaningful. The bandwidth is set
according to the data rate. In general, the jitter is measured over a band of frequencies.
7.0 SERIAL HOST INTERFACE:
A serial microprocessor interface is included in the XRT75L03D. The interface is generic and is designed to
support the common microprocessors/microcontrollers. The XRT75L03D operates in Host mode when the
HOST/HW pin is tied “High”. The serial interface includes a serial clock (SClk), serial data input (SDI), serial
data output (SDO), chip select (CS) and interrupt output (INT). The serial interface timing is shown in Figure
11.
The active low interrupt output signal (INT pin) indicates alarm conditions like LOS, DMO and FL to the
processor.
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