XRT75L03D Datasheet, PDF (130/134 Pages) Exar Corporation – THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

XRT75L03D
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REV. 1.0.0 THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
FIGURE 63. ILLUSTRATION OF THE SUPER PATTERN WHICH IS OUTPUT VIA THE "OC-N TO DS3" MAPPER IC
PATTERN A
PATTERN A
PATTERN B
CROSS-CHECKING OUR DATA
• Each SUPER PATTERN consists of (621 + 621 + 622) = 1864 clock pulses.
• The total amount of time, which is required for the "DS3 to OC-N Mapper" IC to transmit this SUPER
PATTERN is (720 + 720 + 720) = 2160 "STS-1" clock periods.
• This amount to a period of (2160/51.84MHz) = 41,667ns.
• In a period of 41, 667ns, the XRT75L03D (when configured to operate in the DS3 Mode), will output a total
(41,667ns x 44,736,000) = 1864 uniformly spaced DS3 clock pulses.
• Hence, the number of clock pulses match.
APPLYING THE SUPER PATTERN TO THE XRT75L03D
Whenever the XRT75L03D is configured to operate in a "SONET De-Sync" application, the device will accept a
continuous string of the above-defined SUPER PATTERN, via the TCLK input pin (along with the
corresponding data). The channel within the XRT75L03D (which will be configured to operate in the "DS3"
Mode) will output a DS3 line signal (to the DS3 facility) that complies with the "Category I Intrinsic Jitter
Requirements - per Telcordia GR-253-CORE (for DS3 applications). This scheme is illustrated below in Figure
64.
FIGURE 64. SIMPLE ILLUSTRATION OF THE XRT75L03D BEING USED IN A SONET DE-SYNCHRONIZER" APPLICA-
TION
STS-N Signal
De-Mapped (Gapped)
DS3 Data and Clock
DDSS33ttooSSTTSS-N-N
MMaappppeerr//
DDeemmaappppeerr
IICC
TPDATA_n input pin
XXRRTT7755LL0033DD
TCLK_n input
According to this figure, the Jitter Attenuator will receive a very jitter DS3 or E3 signal (e.g., data and clock
signals) from the Mapper device via the "Transmit System-side" input pins of the LIU IC.
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