XRT75L03D Datasheet, PDF (66/134 Pages) Exar Corporation – THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

XRT75L03D
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REV. 1.0.0 THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
TABLE 19: BLOCK LEVEL INTERRUPT ENABLE REGISTER - CR32 (ADDRESS LOCATION = 0X20)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
Channel 2
Interrupt
Enable
Channel 1
Interrupt
Enable
Channel 0
Interrupt
Enable
R/O
R/O
R/O
R/O
R/O
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT
NUMBER
7-3
2
NAME
Unused
Channel 2 Inter-
rupt Enable
1
Channel 1 Inter-
rupt Enable
0
Channel 0 Inter-
rupt Enable
TYPE
R/O
R/W
R/W
R/W
DEFAULT
VALUE
DESCRIPTION
0
0
Channel 2 Interrupt Enable Bit:
This READ/WRITE bit-field is used to do either of the following
• To enable Channel 2 for Interrupt Generation at the Block Level
• To disable all Interrupts associated with Channel 2 within the
XRT75L03D
If the user enables Channel 2-related Interrupts at the Block
Level, then this means that a given Channel 2-related interrupt
(e.g., Change in LOS Defect Condition - Channel 2) will be
enabled if the user has also enabled this particular interrupt at
the Source Level.
If the user disables Channel 2-related Interrupts at the Block
Level, then this means that the XRT75L03D will NOT generate
any Channel 2-Related Interrupts at all.
0 - Disables all Channel 2-related Interrupt.
1 - Enables Channel 2-related Interrupts at the Block Level. The
user must still enable individual Channel 2-related Interrupts at
the source level, before they are enabled for interrupt generation.
0
Channel 1 Interrupt Enable Bit:
Please see the description for Bit 2 Channel 2 Interrupt Enable.
0
Channel 0 Interrupt Enable Bit:
Please see the description for Bit 2 Channel 2 Interrupt Enable.
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