XRT75L03D Datasheet, PDF (123/134 Pages) Exar Corporation – THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

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XRT75L03D
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0
9.7.2 Wander Measurement Test Results
Wander Measurement test results will be provided in the next revision of the XRT75L03D Data Sheet.
9.8 Designing with the XRT75L03D
In this section, we will discuss the following topics.
• How to design with and configure the XRT75L03D to permit a system to meet the above-mentioned Intrinsic
Jitter and Wander requirements.
• How is the XRT75L03D able to meet the above-mentioned requirements?
• How does the XRT75L03D permits the user to comply with the SONET APS Recovery Time requirements of
50ms (per Telcordia GR-253-CORE)?
• How should one configure the XRT75L03D, if one needs to support "Daisy-Chain" Testing at the end
Customer's site?
9.8.1 How to design and configure the XRT75L03D to permit a system to meet the above-
mentioned Intrinsic Jitter and Wander requirements
As mentioned earlier, in most application (in which the XRT75L03D will be used in a SONET De-Sync
Application) the user will typically interface the XRT75L03D to a Mapper device in the manner as presented
below in Figure 57.
In this application, the Mapper has the responsibility of receiving a SONET STS-N/OC-N signal and extracting
as many as N DS3 signals from this signal. As a given channel within the Mapper IC extracts out a given DS3
signal (from SONET) it will typically be applying a Clock and Data signal to the "Transmit Input" of the LIU IC.
Figure 57 presents a simple illustration as to how one channel, within the XRT75L03D should be connected to
the Mapper IC.
FIGURE 57. ILLUSTRATION OF THE XRT75L03D BEING CONNECTED TO A MAPPER IC FOR SONET DE-SYNC APPLI-
CATIONS
STS-N Signal
De-Mapped (Gapped)
DS3 Data and Clock
DDSS33ttooSSTTSS-N-N
MMaappppeerr//
DDeemmaappppeerr
IICC
TPDATA_n input pin
XXRRTT7755LL0033DD
TCLK_n input
As mentioned above, the Mapper IC will typically output a Clock and Data signal to the XRT75L03D. In many
cases, the Mapper IC will output the contents of an entire STS-1 data-stream via the Data Signal to the
XRT75L03D. However, the Mapper IC typically only supplies a clock pulse via the Clock Signal to the
XRT75L03D coincident to whenever a DS3 bit is being output via the Data Signal. In this case, the Mapper IC
would not supply a clock edge coincident to when a TOH, POH or any non-DS3 data-bit is being output via the
Data-Signal.
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