XRT8001 Datasheet, PDF (45/48 Pages) Exar Corporation – WAN Clock for T1 and E1 Systems

XRT8001
3) Both the XRT8001 and XRT8000 can be configured
to accept “Fractional T1/E1” rate clock signals (e.g., K
x 64kHz) and synthesize either a 1.544MHz or
2.048MHz clock signal.
However, the XRT8001 can also synthesize “Frac-
tional T1/E1” rate clock signals, when provided with
either a 1.544MHz or 2.048MHz clock signal
4) The XRT8001 permits the user to determine the
exact role of the LOCKDET output pin. The on-chip
Command Register (within the XRT8001) permits the
user to configure the LOCKDET output pin to have the
functions listed below.
In the XRT8000, the LOCKDET output pin is pulled
HIGH only when both XRT8000 PLLs are “in-lock”.
LOCKDET Pin Function
LOCK Condition of both PLL1 AND PLL2
Description of LOCKDET pin’s role
The LOCKDET output pin toggles “HIGH” only if both (of if the only
enabled) PLLs are “In-LOCK”.
The LOCKDET output pin will toggle “LOW” if any one of the PLLs
are out of LOCK.
NOTE: In this case, the LOCKDET output of the XRT8001
behaves identical to that of the XRT8000.
LOCK Condition of PLL1 Only
The LOCKDET output pin toggles “HIGH” only if PLL1 is in the “In-
LOCK” condition.
LOCK Condition of PLL2 Only
The LOCKDET output pin toggles “HIGH” only if PLL2 is in the “In-
LOCK” condition.
Forced to “LOW”
The LOCKDET output pin is pulled “LOW” regardless of the “Lock”
condition of the two PLLs.
NOTE: The XRT8000 has an additional divide by 8 block which is not included in the XRT8001.
Table 15: Selectable Functions of the LOCKDET Output Pin in the XRT8001
Rev. 1.01
45