XRT8001 Datasheet, PDF (38/48 Pages) Exar Corporation – WAN Clock for T1 and E1 Systems

XRT8001
8.0 Generating 2.048MHz from 1.55MHz
1.544 MHz
Optional
N.C.
1 SDO
SCLK
2
SYNC
8/64 kHz out
CSB
3 FIN
SDI
4 ^GND
Vcc
18
17
16
15 _{+ 5V}
2.048 MHz
+ 5V
+5V
5 GND
GND
14
6 ^CKL1
7 V_CC
CLK
13 _N.C.
2
V_CC
12 _{+ 5V}
8 ^MSB
LOCKDET ¹¹
9 ^GND
V_CC
10 _{+ 5V}
Optional
Clock and Data In
Reset
Busy
VER_REQ
VER_PASS/FAIL
PLD
or µP
Serial Port Control
Figure 22. Typical Application Example: Generating 2.048MHz from 1.544MHz
Serial Port Programming in Four Steps
Step
Procedure
1
Set the "MSB_OUT" output pin to "high"
2
Write the value "00101" into Command
Register CR0 (located at 0x00)
3
Write the value "00000" into Command
Register CR1 (located at 0x01)
4
Write the value "11111" into Command
Register CR2 (located at 0x02)
5
Write the value "01000" into Command
Register CR4 (located at 0x04)
Result
Configures XRT8001 to operate in "Master" mode
Configures XRT8001 to accept an "N x 1.544MHz clock
signal via the "FIN" input pin., and output a "K x 64kHz"
clock signal via the "CLK1" output pin. (For this
application N = 1 and K = 32). This step also enables
"PLL #1" within the XRT8001
Sets "N" (as in "N x 1.544MHz") to be "1"
Sets "K" (as in "K x 64kHz") to be "32"
Enables the output driver for CLK1
Rev. 1.01
38