XRT8001 Datasheet, PDF (19/48 Pages) Exar Corporation – WAN Clock for T1 and E1 Systems

XRT8001
In the “High Speed – Reverse” Mode
In the “High Speed – Reverse” Mode, the XRT8001
WAN Clock will be receiving a 64kHz clock signal via
the “FIN” input pin. The XRT8001 WAN Clock will, in
response, generate an “M x 2.048MHz” clock via the
CLK1 and CLK2 output pins. These five (5) bit-fields
within Command Register CR2 are used to define the
value “M” for the CLK1 output.
Note: The only acceptable values for “M” are 1, 2, 4, or 8.
3.2.4 Command Register CR3 (Address = 0x03)
D4 – D0 (SEL2[4:0])
These bit-fields are used to support configuration
implementation for the “Forward/Master” and the “High
Speed – Reverse” Modes of operation.
In the “Forward/Master” Mode
In the “Forward/Master” Mode, the XRT8001 WAN
Clock will output either a “K x 56kHz” or a “K x 64kHz”
clock signal via the CLK2 output pin. These five (5) bit-
fields within Command Register CR3 are used to define
the value of “K” for the CLK2 Output. As a conse-
quence, the XRT8001 can be configured to generate a
maximum frequency of “32 x 56kHz” or “32 x 64kHz” via
the CLK2 output pin.
In the “High Speed – Reverse” Mode
In the “High Speed – Reverse” Mode, the XRT8001
WAN Clock will be receiving a 64kHz clock signal via
the “FIN” input pin. The XRT8001 WAN Clock will, in
response, generate an “M x 2.048MHz” clock via the
CLK1 and CLK2 output pins. These five (5) bit-fields
within Command Register CR3 are used to define the
value “M” for the CLK2 output.
3.2.5 Command Register CR4 (Address = 0x04)
D4 – SYNCEN (SYNC Output Driver Enable Select)
This “read/write” bit-field permits the user to enable or
disable the Driver associated with the SYNC output
pin. Setting this bit-field to “1” enables this Driver.
Setting this bit-field to “0” disables this Driver.
D3 – CLK1EN (CLK1 Output Driver Enable Select)
This “read/write” bit-field permits the user to enable or
disable the Driver associated with the CLK1 output pin.
Setting this bit-field to “1” enables this Driver. Setting
this bit-field to “0” disables this Driver.
D2 – CLK2EN (CLK2 Output Driver Enable Select)
This “read/write” bit-field permits the user to enable or
disable the Driver associated with the CLK2 output pin.
Setting this bit-field to “1” enables this Driver. Setting
this bit-field to “0” disables this Driver.
D1,D0–LDETDIS[2:1]–LockDetectorOutput Control
The combination of these two bit-fields permit the user
to specify the signal that will be output via the
LOCKDET output pin. The user’s options are shown in
Table 3.
Note: The only acceptable values for “M” are 1, 2, 4, or 8.
Rev. 1.01
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