XRT8001 Datasheet, PDF (16/48 Pages) Exar Corporation – WAN Clock for T1 and E1 Systems

XRT8001
3.0 Description of the Command Registers
3.1 Address Map of the "On-Chip" Command
Registers
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
Command
Register
CR0
CR1
CR2
CR3
CR4
CR5
CR6
CR7
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
D4
IOC4
M4
SEL14
SEL24
SYNCEN
Reserved
Reserved
Reserved
Register Bit-Format
D3
D2
D1
IOC3
M3
SEL13
SEL23
CLK1EN
Reserved
Reserved
Reserved
IOC2
M2
SEL12
SEL22
CLK2EN
Reserved
Reserved
Reserved
IOC1
M1
SEL11
SEL21
LDETDIS2
Reserved
Reserved
Reserved
D0
PL1EN
PL2EN
SEL10
SEL20
LDETDIS1
Reserved
Reserved
Reserved
3.2 Command Register Description
3.2.1 Command Register CR0 (Address = 0x00)
D4 – D1 (Configuration Mode Select Bits)
These four-bit fields permit the user to select which
mode the XRT8001 will operate in. Specifically, these
four bit-fields make the following configuration selec-
tions:
1. Whether the XRT8001 will be operating in the
“Forward/Master”, “Reverse/Master”, “Fractional
T1/E1 Reverse/Master”, "E1 to T1 - Forward/Mas-
ter" and “High Speed - Reverse” odes.
2. What kind of input signals are to be applied to the
Reference Clock Input (FIN).
3. What kind of signals will be output via the CLK1
and CLK2 output pins.
Table 2A relates the value of these four bit-fields to the
four Master Modes and Table 2B relates to the three
Slave Modes of the XRT8001.
Rev. 1.01
16