XRT8001 Datasheet, PDF (35/48 Pages) Exar Corporation – WAN Clock for T1 and E1 Systems

XRT8001
7.0 Phase Relationship Between SYNC and CLK1 0r
CLK2
Table 11, presents information on the delay between
the rising edge of SYNC and CLK1 or CLK2 output
signals. It is important to Note that this delay behaves
as a function of the settings within the CR3 register.
SEL14~SEL10
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
t Values (nS)
K
Kx56 MODE
1
372
2
372
3
372
4
372
5
446
6
372
7
319
8
279
9
496
10
446
11
406
12
372
13
343
14
319
15
298
16
279
17
525
18
496
19
470
20
446
21
425
22
406
23
388
24
372
25
357
26
343
27
331
28
319
29
308
30
298
31
288
32
279
Kx64 MODE
326
326
326
326
391
326
279
244
434
301
355
326
301
279
260
244
460
434
411
391
372
355
340
326
312
301
289
279
279
260
252
244
Table 11. Delay Time Between SYNC and CLK1 or CLK2
Note:
This table only applies when the XRT8001 is configured
to operate in the "Forward/Master" or "Forward/Slave"
Modes.
Rev. 1.01
35